P. Chandraiah, R. Doemer: “Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1078-1090, June 2008.
S. Pasricha, N. Dutt, M. Ben-Romdhane, “BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol.26, no.8, pp.1454-1464, August 2007.
E. Bozorgzadeh, S. Ghiasi, and M. Sarrafzadeh, “Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol. 23, No. 8, pp 1184- 1199 , August 2004.
download pdf
E. Bozorgzadeh, R. Kastner, and Majid Sarrafzadeh, “Creating and Exploiting Flexibility in Rectilinear Steiner Trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 605-615, Vol. 22, No. 5, May 2003.
download pdf
Q. Zhang and I. G. Harris, “Partial BIST Insertion to Eliminate Data Correlation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003.
download pdf
T. Givargis and F. Vahid, “Platune: A Tuning Framework for System-on-Chip Platforms,” IEEE Transactions on Computter-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 11, November 2002, pp 1317-1327.
I. G. Harris and R. Tessier, “Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 21, No. 11, November 2002.
download pdf
R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 777-790, vol. 21, No. 7, July 2002.
download pdf
I. Bayraktaroglu and A. Orailoglu, “Concurrent Test for Digital Linear Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9, September 2001, pp 1132-1142.