J. Peng, A. Gerstlauer, R. Doemer, D. Gajski, "System-On-Chip Architecture Modeling Style Guide," TR 04-22, July 31, 2004. download pdf P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, P. Ienne, "ISEGEN: Adapting Kernighan-Lin Min-Cut Heuristic for Generation...
P. Mishra and N. Dutt, "Functional Coverage Driven Test Generation for Validation of Pipelined Processors," TR 04-05, March 12, 2004. download pdf
S. Pasricha, N. Dutt, and M. Ben-Romdhane, " Automated Synthesis of Bus Architectures for Systems with Throughput Constraints," TR 04-20, August 2004. download pdf
L. Cai, A. Gerstlauer, and D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," TR 04-04, February 2004. download pdf
R. Doemer, A. Gerstlauer, D. Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," TR 04-19, July 22, 2004. download pdf
