S. Cotterell, R. Mannion, F. Vahid, H. Hsieh, “eBlocks – An Enabling Technology for Basic Sensor Based Systems,” IPSN Track on Sensor Platform, Tools and Design Methods for Networked Embedded Systems (SPOTS), April 2005.download pdf
C. Park, J. Liu, and P. Chou , “Eco: an Ultra-Compact Low-Power Wireless Sensor Node for Real-Time Motion Monitoring ,” IEEE/ACM International Conference on Information Processing in Sensor Networks (IPSN), April 2005.download pdf
M.Kim, H. Oh, N.Dutt, A.Nicolau, and N.Venkatasubramanian, “Probability Based Power Aware Error Resilient Coding,”(ICDCS’05) Workshop on Services and Infrastructures for the Ubiquitous and Mobile Internet (SIUMI’05), June 2005.
International Conference on High Performance Computing (HiPC 2005)
B. Gorjiara, D. Gajski, “Design Space Exploration of C Programs Using NISC: A Case-Study on DCT algorithm,” IEEE workshop on Embedded Systems for Real-Time Multimedia, April 2005. download pdf
A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt and R. Gupta, “Energy Analysis of Multimedia Watermarking in Mobile Handheld Devices,” IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), April 2005. download pdf
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2005 (CASES 2005)
H. Oh, N. Dutt, S. Ha, “Single Appearance Schedule with Dynamic Loop Count for the Minimum Data Buffer from Synchronous Dataflow Graphs,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf
M. Ghodrat,T. Givargis, A. Nicolau, “Equivalence Checking of Arithmetic Expressions Using Fast Evaluation,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf
A. Shrivastava, I. Issenin, N. Dutt, “Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.download pdf
S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, “Floorplan-aware Automated Synthesis of Bus-based Communication Architectures,” Design and Automation Conference (DAC 2005), June 2005. download pdf
S. Banerjee, E. Bozorgzadeh, N. Dutt, “Physically-aware HW-SW Partitioning for reconfigurable architectures with partial dynamic reconfiguration,” Design Automation Conference (DAC 2005), June 2005.
Design, Automation and Test in Europe Conference (DATE 05)
R. Lysecky, and F. Vahid, “A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores Using Dynamic Hardware/ Software Partitioning,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 18-23, March 7-11 2005 download pdf
A. Ghosh and T. Givargis, “LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 190-195, March 7-11 2005 download pdf
S. Abdi and D. Gajski, “Functional Validation of System Level Static Scheduling,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 542-547, March 7-11 2005 download pdf
P. Mishra and N. Dutt, “Functional Coverage Driven Test Generation for Validation of Pipelined Processors,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 678-683, March 7-11 2005 download pdf
A. Nacul and T. Givargas, “Lightweight Multitasking Support for Embedded Systems Using the Phantom Serialized Compiler,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany pp 742-747, March 7-11 2005 download pdf
S. Zhao and D. Gajski, “Defining an Enhanced RTL Semantics,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 548-553,, March 7-11 2005 download pdf
M. Reshadi and N. Dutt, “Generic Pipelined Processor Modeling and Cycle-Accurate Simulation Generation,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 786-791, March 7-11 2005 download pdf
I. Issenin and N. Dutt, “FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 808-813, March 7-11 2005 download pdf
R. Mannion, H. Hsieh, S. Cotterell and F. Vahid, “System Synthesis for Networks of Programmable Blocks,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 888-893, March 7-11 2005 download pdf
P.Biswas, S. Banerjee, N. Dutt, L. Pozzi and P. Ienne, “ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 1246-1251, March 7-11 2005 download pdf
A. Shrivastava, N. Dutt, A. Nicolau and E. Earlie, “PBEXPLORE: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors,”Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 1264-1270, March 7-11 2005 download pdf
G. Stitt and F. Vahid, “A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms Minimization,” Proceedings of the Design, Automation and Test in Europe Conference (DATE 05), Messe Munich, Germany, pp 396-397 , March 7-11 2005 download pdf
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2005)
M. Reshadi, D. Gajski, “A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf
A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau, “Aggregating Processor Free Time for Energy Reduction,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf
D. Shin, A. Gerstlauer, R. Dömer, and D. Gajski, “Automatic Network Generation for System-on-Chip Communication Design,” International Conference on Hardware/Software Codesign and System Synthesis, September 2005.download pdf
International Conference on Computer Design (ICCD 2005)
M. Reshadi, B. Gorjiara, D. Gajski, “Utilizing Horizontal and Vertical Parallelism with No-Instruction-Set Compiler for Custom Datapaths,” International Conference on Computer Design (ICCD), October 2005.download pdf
M. Ramirez, A. Cristal, A. Veidenbaum, L. Villa, M. Valero, “A New Pointer-based Instruction Queue and Its Power-Performance Evaluation,” International Conference on Computer Design (ICCD 2005), October 2005. Best Paper Award at ICCD 2005
Symposium on Principles and Practice of Parallel Programming (PPoPP)
A. Kejariwal, A. Nicolau, U. Banerjee and C. D. Polychronopoulos, “A Novel Approach for Partitioning Iteration Spaces with Variable Densities,” Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2005.download pdf
ACM International Symposium on Field-Programmable Gate Arrays (FPGA)
S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R.Kastner, and E. Bozorgzadeh, “HARP:Hard-wired Routing Pattern FPGAs,” ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2005. download pdf
G. Stitt, Z. Guo, F. Vahid, and W. Najjar, “Techniques for Synthesizing Binaries to an Advanced Register/Memory Structure,” ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2005. download pdf
International Symposium on High Performance Computing (ISHPC- VI)
P.D’Alberto and A. Nicolau, “Using Recursion to Boost ATLAS’s Performance,” International Symposium on High Performance Computing (ISHPC-VI), September 2005.download pdf
A. Kejariwal, A. Nicolau and C. Polychronopoulos, “Enhanced Loop Coalescing: A Compiler Technique for Transforming Non-Uniform Iteration Spaces,” International Symposium on High Performance Computing (ISHPC-VI), September 2005.
D. Nicolaescu, A. Veidenbaum, A. Nicolau, “Using a Way Cache to Improve Performance of Set-Associative Caches,” International Symposium on High Performance Computing (ISHPC-VI), September 2005.
International Workshop on Advanced Parallel Programming Technologies (APPT 2005)
Location: Hong Kong, China
C. Liu and J-L Gaudiot, “Static Partitioning vs Dynamic Sharing of Resources in Simultaneous Multi-Threading Microarchitectures,” International Workshop on Advanced Parallel Programming Technologies (APPT 2005), October 27-28, 2005. download pdf
International Conference on Modeling, Simulation, and Visualization Methods (MSV 2005)
T. Harmon and R. Klefstad, “VADRE: A Visual Approach to Performance Analysis of Distributed, Real-Time Systems,” International Conference on Modeling, Simulation, and Visualization Methods, June 27-30 2005.
