Conference Proceedings

Asia South Pacific Design Automation Conference 2005 Shanghai China (ASP-DAC 2005)

Location: Shanghai, China
Web Site: http://www.aspdac.com/

S. Abdi and D. Gajski, “A Formalism for Functionality Preserving System Level Transformations,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 139-144, January 18-21, 2005 download pdf

Y. Agarwal, C. Schurgers, and R. Gupta, “Dynamic Power Management Using On-Demand Paging for Networked Embedded Systems,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 755-759, January 18-21, 2005 download pdf

R. Ayoub and A. Orailoglu, ” A Unified Transformational Approach for Reductions in Fault Vulnerability, Power, and Crosstalk Noise and Delay on Processor Buses,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 729-734, January 18-21, 2005 download pdf

L. Cai, A. Gerstlauer,  and D. Gajski, “Multi-Metric and Multi-Entity Characterization of Applications for Early System Design Exploration,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 944-947, January 18-21, 2005 download pdf

A. Gerstlauer, D. Shin, R. Doemer, and D. Gajski, “System-Level Communication Modeling for Network-on-Chip Synthesis,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 45-48, January 18-21, 2005 download pdf

S. Pasricha, N. Dutt, and M. Ben-Romdhane, “Automated Throughput-Driven Synthesis of Bus-Based Communication Architectures,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 495-498, January 18-21, 2005 download pdf

J. Peng, S. Abdi, and D. Gajski, “A Clustering Technique to Optimize hardware/Software Synchronization,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 965-968, January 18-21, 2005 download pdf

W. Rao, A. Orailoglu, and R. Karri, “Fault Tolerant Nanoelectronic Processor Architectures,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 311-316, January 18-21, 2005 download pdf

J. Seo and N. Dutt, “A Generalized Technique for Energy-Efficient Operating Voltage Set-Up in Dynamic Voltage Scaled Processors,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 836-841, January 18-21, 2005 download pdf

R. Topaloglu and A. Orailoglu, “Forward Discrete Probability Propagation Method for Device Performance Characterization Under Process Variations,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 220-223, January 18-21, 2005 download pdf

S. Verma, K. Ramineni, and I. Harris, “An Efficient Control-Oriented Coverage Metric,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 317-322, January 18-21, 2005 download pdf
T. Wei, K. Wu, R. Karri, and A. Orailoglu, “Fault Tolerant Quantum Cellular Array (QCA) Design Using Triple Modular Redundancy with Shifted Operands,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 1192-1195, January 18-21, 2005 download pdf

C. Zhang and F. Kurdahi, “On Combining Iteration Space Tiling with Data Space Tiling for Scratch-Pad Memory Systems,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 965-968, January 18-21, 2005 download pdf

 

International Embedded Systems Symposium (IESS 2005)

Location: Manaus, Brazil
Web Site: http://www.iess.org/

G. Schirner and R. Dömer, “Abstract Communication Modeling: A Case Study Using the CAN Automotive Bus,” International Embedded Systems Symposium, August 2005. (Best Paper Award)download pdf

H. Yu, R. Dömer, and D. Gajski, “Software and Driver Synthesis from Transaction Level Models,”Proceedings of the International Embedded Systems Symposium, August 2005.download pdf

D. Shin, A. Gerstlauer, R. Dömer, and D. Gajski “Automatic Generation of Communication Architectures,” Proceedings of the International Embedded Systems Symposium, August 2005.download pdf

 

International Conference on Computer Aided Design (ICCAD)

Location: San Jose, CA
Web Site: http://www.iccad.com/

L. Singhal and E. Bozorgzadeh, “Fast Timing Closure Through Interconnect Criticality Driven Delay Relaxation,” International Conference on Computer-Aided Design (ICCAD) , November 2005. download pdf

P. Chou and C. Park, “Energy Efficient Platform Designs for Real-World Wireless Sensing Applications,” International Conference on Computer Aided Design (ICCAD), November 2005.

 

NSTI Nanotechnology Conference 2005

Web Site: http://www.nsti.org/Nanotech2005/

S. Hiyama, Y. Moritani, T. Suda, R. Egashira, A. Enomoto, M. Moore, and T. Nakano, “Molecular Communication,” NSTI Nanotech, May 8-12, 2005.

 

International Conference on Universal Access in Human-Computer Interaction (UAHCI 2005)

Web Site: http://www.hci-international.org/

D. Billsus, R. Klefstad, M. J. Pazzani, “Adaptive Personalization for Mobile Content Delivery,” International Conference on Universal Access in Human-Computer Interaction, July 22-27, 2005.

 

International Conference on Sensing Technologies (ICST 2005)

Location: Palmerston North, New Zealand
Web Site: http://icst.massey.ac.nz/

J. Lu, L. Bao, and T. Suda, “Probabilistic Self-Scheduling for Coverage Configuaration in Sensor Networks,” International COnference of Sensing Technology, November 21-23 2005. download pdf

 

IEEE International Symposium on Circuits and Systems (ISCAS 2004)

Location: Vancouver, Canada
Web Site: http://www.iscas2004.org/

A. Yazdi and P. Heydari, “A Novel Non-Uniform Distributed Amplifier,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

A. Safarian and P. Heydari, “Design and and Analysis of a Distributed Regenerative Frequency Divider Using a Distributed Mixer,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

Ravindran Mohanavelu and Payam Heydari, “A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

 

Design Automation Conference 2004 (DAC 2004)

Location: San Diego, CA
Web Site: http://www.dac.com/

S. Abdi and D. Gajski, “Automatic Generation of Equivalent Architecture Model from Functional Specification,” Design and Automation Conference (DAC 2004), pp 608-613, June 7-11, 2004 download pdf

P. Biswas, V. Choudhary, K. Atasu, L. Pozzi, P. Ienne, and N. Dutt, “Introduction of Local Memory Elements in Instruction Set Extensions,” Design and Automation Conference (DAC 2004), pp 729-734, June 7-11, 2004 download pdf
L. Cai, A. Gerstlauer, and D. Gajski, “Retargetable Profiling for Rapid, Early System-Level Design Space Exploration,” Design and Automation Conference (DAC 2004), pp 281-286, June 7-11, 2004

R. Jejurikar, C. Pereira, and R. Gupta, “Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems,” Design and Automation Conference (DAC 2004), pp 275-280, June 7-11, 2004

A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt and R. Gupta, “Proxy-Based Task Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices,” Design and Automation Conference (DAC 2004), pp 556-561, June 7-11, 2004 download pdf

R. Lysecky, F. Vahid, and S. Tan, “Dynamic FPGA Routing for Just-in-Time FPGA Compilation,” Design and Automation Conference (DAC 2004), pp 659-662, June 7-11, 2004 download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration,” Design and Automation Conference (DAC 2004), pp 113-118, June 7-11, 2004 download pdf

 

International Conference on Embedded and Reconfigurable Systems and Architecture

E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, “Incremental Timing Budget Management in Programmable Systems,” International Conference on Embedded and Reconfigurable Systems and Architecture, July 2004. download pdf

 

International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004)

Location: Stockholm, Sweden
Web Site: http://www.codes-isss.org/

S. Banerjee and N. Dutt, “Efficient Search Space Exploration for HW-SW Partitioning,” CODES+ISSS 2004, Stockholm, Sweden, pp 122-127, September 8-10, 2004 download pdf

M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, ” Analytical Models for Leakage Power Estimation of Memory Array Structures,” CODES+ISSS 2004,”Stockholm, Sweden, pp 146-151, September 8-10, 2004 download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based On-chip Communication Architectures,” CODES+ISSS 2004, Stockholm, Sweden, pp 242-247, September 8-10, 2004 download pdf

F. Rivera, M. Sanchez-Elez, M. Fernandez, R. Hermida, and N. Bagherzadeh, “Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures,” CODES+ISSS 2004, Stockholm, Sweden, pp 30-35, September 8-10, 2004 download pdf

A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau, “Operation Tables for Scheduling in the Presence of Incomplete Bypassing,” CODES+ISSS 2004, Stockholm, Sweden, pp 194-199, September 8-10, 2004 download pdf

 

ACM/IEEE International Conference on Computer-Aided Design

Location: San Jose, CA
Web Site: http://www.iccad.com/

S. Ghiasi, S. Choudhuri, E. Bozorgzadeh, M. Sarrafzadeh, “A Unified Theory for Timing Budget Management,” ACM/IEEE International Conference on Computer-Aided Design, November 2004. download pdf

 

Design, Automation and Test in Europe Conference (DATE ‘04)

Location: Paris, France
Web Site: http://www.date-conference.com/

J. Aragon, D. Nicolaescu, A. Veidenbaum, and A. Badulescu, “Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1374-1375, February 16-20, 2004

B. Arslan and A. Orailoglu, “Circular-Scan: A Scan Architecture for Test Cost Reduction,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1290-1295, February 16-20, 2004

N. Bansal, S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 474-479, February 16-20, 2004

A. Gordon-Ross, F. Vahid, and N. Dutt, “Automatic Tuning of Two-Level Caches to Embedded Applications,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 208-213, February 16-20, 2004

S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 114-120, February 16-20, 2004

M. Heath, W. Burleson, and I. G. Harris, “Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC,” IEEE/ACM Design Automation and Test in Europe Conference (DATE ’04), Paris, France, February 16-20, 2004 download pdf

R. Lysecky, and F. Vahid, “A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 480-485, February 16-20, 2004

P. Mishra, N. Dutt, “Graph-Based Functional Test Program Generation for Pipelined Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 182-187, February 16-20, 2004

A. Nacul and T. Givargas, “Dynamic Voltage and Cache Reconfiguration for Low Power,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1376-1378, February 16-20, 2004

O. Sinanoglu and A. Orailoglu, “Scan Power Minimization Through Stimulus and Response Transformations,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 404-409, February 16-20, 2004

C. Zhang and F. Vahid, “Using a Victim Buffer in an Application-Specific Memory Hierarchy,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 220-227, February 16-20, 2004

C. Zhang, F. Vahid, and R. Lysecky, “A Self-Tuning Cache Architecture for Embedded Systems,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 142-147, February 16-20, 2004

C. Zhang, J. Yang, and F. Vahid, “Low Static-Power Frequent-Value Data Caches,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 214-219, February 16-20, 2004

 

Asia South Pacific Design Automation Conference 2004 Pacifico Yokohama (ASP-DAC 2004)

Location: Yokohama, Japan
Web Site: http://www.aspdac.com/

S. Abdi and D. Gajski, “On Deriving Equivalent Architecture Model from System Specification,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 322-327, January 27-30, 2004

L. Cai, H. Yu and D. Gajski, “A Novel Memory Size Model for Variable-Mapping in System Level Design,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 813-818, January 27-30, 2004

B. Gorji-Ara, P. Chou, N. Bagherzadeh, M. Reshadi and D. Jensen, “Fast and Efficient Voltage Scheduling by Evolutionary Slack Distribution,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 659-662, January 27-30, 2004

P. Heydari, “High-Frequency Noise in RF Active CMOS Mixers,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 57-61, January 27-30, 2004 download pdf

D. Shin, S. Abdi, and D. Gajski, “Automatic Generation of Bus Functional Models from Transaction Level Models,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 756-758, January 27-30, 2004

A. Shrivastava and N. Dutt, “Energy Efficient Code Generation Exploiting Reduced Bit-Width Instruction Set Architectures (rISA),”Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 475-477, January 27-30, 2004

O. Sinanoglu and A. Orailoglu, “Efficient RT-Level Fault Diagnosis Methodology,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 212- 217, January 27-30, 2004

R. Topaloglu and A. Orailoglu, “On Mismatch in the Deep Sub-Micron Era – From Physics to Circuits,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 62-67, January 27-30, 2004

H. Yu, R. Doemer and D. Gajski, “Embedded Software Generation from System-Level Design Languages,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 463-468, January 27-30, 2004

 

CODES + ISSS

L. Cai and D. Gajski, “A Transaction Level Modeling: An Overview,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 19-24,Newport Beach, CA, October 2003
download pdf :: download slide presentation

S. Cotterell, F. Vahid, W. Najjar and H. Hsieh, “First Results with eBlocks: Embedded Systems Building Blocks,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 168-175 Newport Beach, CA, October 2003 download pdf

A. Koohi, N. Bagherzadeh, and C. Pan, “A Fast Parallel Reed-Solomon Decoder on a Reconfigurable Architecture,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 59-64,Newport Beach, CA, October 2003 download pdf

B. Mohebbi, E. Filho, R. Maestre, M. Davies, and F. Kurdahi, “A Case Study of Mapping a Software Defined Radio (SDR) Application on a Reconfigurable DSP Core,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 103-108, Newport Beach, CA, October 2003 download pdf

M. Reshadi, N. Bansa, P. Mishra and N. Dutt, “An Efficient Retargetable Framework for Instruction-Set Simulation,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 13-18, Newport Beach, CA, October 2003 download pdf

H. Yu, A. Gerstlauer, and D. Gajski, “RTOS Scheduling in Transaction Level Models,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 31-36, Newport Beach, CA,October 2003 download pdf

 

International Conference on Computer Design (ICCD 2003

S. Pasricha, and A. Veidenbaum, “Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches,” International Conference on Computer Design (ICCD 2003), San Jose, CA, October 2003 download pdf