D. Shin, D. D. Gajski, "Queue Generation Algorithm for Interface Synthesis," TR 02-12, April 11, 2002. download pdf
Scheduling in RTL Design Methodology
D. Shin, D. D. Gajski, "Scheduling in RTL Design Methodology," TR 02-11, April 12, 2002. download pdf
Optimal Indexing for Cache Miss Reduction in Embedded Systems
T. Givargis, "Optimal Indexing for Cache Miss Reduction in Embedded Systems," TR 02-10, July 4, 2002. download pdf
RTL Design and Synthesis of Sequential Matrix Multiplication
P. Zhang, D. D. Gajski, "RTL Design and Synthesis of Sequential Matrix Multiplication," TR 02-09, April 3, 2002. download pdf
System Level Design Using SpecC Profiler
L. Cai, D. D. Gajski, "System Level Design Using SpecC Profiler," TR 02-08, April 1, 2002. download pdf
Introduction of Design-Oriented Profiler of SpecC Language
L. Cai,D. D. Gajski, "Introduction of Design-Oriented Profiler of SpecC Language," TR 02-07, March 1, 2002. download pdf
Parity Checker Implementations in SpecC
Q. Xie, D. D. Gajski, "Parity Checker Implementations in SpecC," TR 02-06, January 27, 2002. download pdf
Datapath Synthesis for a 16-Bit Microprocessor
H. Yu, D. D. Gajski, "Datapath Synthesis for a 16-Bit Microprocessor," TR 02-05, January 22, 2002. download pdf
The Formal Execution Semantics of SpecC
W. Mueller, R. Doemer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," TR 02-04, January 11, 2002. download pdf
Efficiency and Optimality of Static Slowdown for Periodic Tasks in Real-Time Embedded Systems
R. Jejurikar, R. Gupta, "Efficiency and Optimality of Static Slowdown for Periodic Tasks in Real-Time Embedded Systems," TR 02-03, March 19, 2002. download pdf