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Secure VLSI Test Methods

Secure VLSI Test Methods

Speaker Dr. Ramesh Karri
Polytechnic University
CECS Host Ian Harris
Location Donald Bren Hall (DBH) 3011
Date & Time June 15 , 2010
Refreshments at 10:30 am; Lecture begins at 11:00 am
Abstract Design for Test (DFT) techniques improve access to the internal state of hardware either by improving control of internal nodes from the primary inputs or by improving observation of values on internal nodes at the primary outputs or both. On the other hand, from a security perspective, hardware should minimize controllability and observability of the internal state to a minimum. In this talk we will discuss our research on secure DFT architectures that reconcile Testability and Security.

Ramesh Karri is an Associate Professor in the Department of Electrical and Computer Engineering. Prof. Karriā€™s research interests are in the areas of secure hardware design, computer-aided secure hardware design, high-speed architectures for network protocols and encryption, and computer-aided design of fault-tolerant nanoscale systems.

Prof. Karri is the recipient of an NSF CAREER award, an Alexander Humboldt Fellowship and several grants including from the National Science Foundation, the Air Force Research Labs and Army. Most recently, Prof. Karri has been a co-PI with Program Director Nasir Memon on the just-awarded $2.124 million NSF grant from the National Science Foundation research and teaching of security and privacy issues on the Internet and other critical information infrastructure and is a founding member of the Center for Research in Interdisciplinary Studies in Security and Privacy at NYU.

Professor Karri received his MS in Computer Engineering at the University of California (1992), and his PhD in Computer Science also at the University of California (1993).