Payam Heydari, associate professor of electrical engineering and computer science, and a Calit2 academic affiliate at UC Irvine, has won this year’s prestigious Guillemin- Cauer Award from the IEEE Circuits and Systems Society. Heydari is also the recipient of the 2005 IEEE Circuits and Systems Society Darlington Award, which puts him in an elite group of only seven researchers who, in the 40-year history of the awards, have received both.
Heydari was recognized for his paper “Model-Order Reduction Using Variational Balanced Truncation with Spectral Shaping,” which was published in the IEEE Transactions on Circuits and Systems, Vol. 53, April 2006.
The latest integrated circuit technology – geared to the nanoscale – continues to create new possibilities for designers to substantially reduce chip size and increase speed. The technology, however, also presents challenges, most notably to the yield and reliability of the circuits and on-chip wires.
It is essential to capture statistical fluctuations caused by process variations, but testing such complicated systems can require days of computer simulation. Heydari’s approach dramatically reduces the time needed for this statistical modeling from days to just minutes. It significantly reduces the order of the original system while retaining important circuit characteristics, such as frequency and timedomain. Most notably, this technique accounts for statistical variation due to changes in process.
In addition, Heydari’s approach provides a proven boundary for error between the reduced order model and the original system. The work has since been the foundation for several key papers published by other researchers on the same topic.
The Guillemin-Cauer Award recognizes the best journal paper published in IEEE Transactions on Circuits and Systems during the two calendar years preceding the award. The award is based on general quality, originality, contributions, subject matter and timeliness.