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No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract

September 18, 2007 @ 3:00 pm - 4:00 pm PDT

No-Instruction-Set-Computer (NISC) Modeling and Compilation Abstract

by Mehrdad Reshadi

Today, depending on the size and complexity of a program, there are two options for synthesizing a program to hardware: (1) using High Level Synthesis (HLS), and (2) using Application-Specific-Instruction-Processor (ASIP).

Traditional HLS techniques can only support relatively small applications and do not give enough control to the designer over the quality of results. Poor quality of results and limited application domain has prevented the HLS from wide spread usage.

Embedded processors often run only one or a few applications in the life-time of the system. Therefore, they can be customized for the target applications and significantly improve the quality of the embedded system in terms of cost, performance, power consumption, etc. This is the goal in ASIP approaches. Instruction-based architectures limit the customizations because: (a) hardware designer is limited by instruction coding, size and complexity of the decoder; (b) compilers can support certain class of instructions and hence instructions cannot be very complex; and (c) manually updating compilers to incorporate the custom instructions is not practical and developing compilers that automatically utilize hardware customizations through new custom instructions is very complex.

In this talk I present a new design approach called NISC (No-Instruction-Set-Computer) Technology. In NISC, the datapath and controller are generated in two different phases. First the datapath is generated or selected from a database based on the application behavior. At the core of NISC technology, there is a cycle-accurate compiler that maps a given application directly on a given datapath and generates the control words (CWs) that control the datapath resources in every clock cycle. The NISC architecture style is similar to the old nanocode machines. However, instead of using nanocodes inside the process for implementing the microcodes and in turn instructions, in NISC the nanocode (CWs) are directly used to program the datapath.

NISC simplifies customization and allows designer to fully control design quality. NISC simplifies ASIP (Application-Specific-Instruction-Processor) approach by removing the complex task of finding and designing “most profitable” custom instructions. In NISC only the datapath needs to be specified and NISC compiler generates code “as if” each basic block of the program is executed with one custom instruction. On the other hand, NISC improves resource constrained HLS techniques by adding the connectivity constraints, on top of the traditional resource constraints, into synthesis process. This enables the designer to control every thing in datapath including wires, which are becoming increasingly more critical in newer technologies. In fact NISC combines the ASIP and HLS techniques.

To realize the NISC Technology design flow, several challenging categories of problems must be solved. Mainly we need:

1. Techniques for efficiently designing and customizing a datapath for an application
2. Techniques for efficiently compiling any application on any given datapath
3. Techniques for efficiently synthesizing a controller from the output of compiler and then generating synthesizable code for different target implementations.

In my thesis, I focus on the compilation problems to enable practical use of NISC IPs in a system. A working compiler and other NISC tools are available for public use from NISC websitehttps://www.cecs.uci.edu/~nisc/. An online version of the tools can be also directly accessed at this website.


September 18, 2007
3:00 pm - 4:00 pm PDT
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