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High Level Synthesis – Some Challenging Problems
November 5, 2016 @ 3:00 pm - 4:00 pm PDT
Title: “High Level Synthesis – Some Challenging Problems”
Speaker: George A. Constantinides, Imperial College London, UK
Date and Time: Wednesday, November 16, 2016 at 11:00 A.M.
Location: Engineering Hall 2430
Host: Professor Nikil Dutt
Abstract: High Level Synthesis – synthesis of circuits from behavioral descriptions – is a long-standing problem, but one that appears to now have come to age. Both the demand for, and the supply of, quality HLS tools is now in place. However, there are still some hard problems to be overcome in order to make HLS fully general. My research focuses on two of these: customization of memory systems to algorithms, and customization of number representation to algorithms. After briefly introducing the work at Imperial – and encouraging PhD and postdoc applications (!) – I will spend a little time on each of these problems. In particular, I will look at the problem of customization of memory for heap manipulating programs, the potential of parametric analysis for synthesis of lightweight run-time scheduling changes, and automates code refactoring for rigorously controlled accuracy / latency / area optimization. I hope to inspire the audience to consider how you may be able to contribute to these problems.
Biography: Prof George A. Constantinides holds the Royal Academy of Engineering / Imagination Technologies Chair in Digital Computation at Imperial College London, where he leads the Circuits and Systems research group. He has been a member of staff at Imperial since 2001. Over this time he has been the proud supervisor of 25 graduated PhD students and chaired the FPGA, FPT, and FPL conferences. He enjoys hard problems and espresso.