Customizable Embedded Processor Architectures
Department of Computer Science and Engineering
University of California, San Diego, CA
|CECS Host||Professor Jean-Luc Gaudiot
|Location||McDonnell Douglas Auditorium|
|Date & Time||April 14, 2005
Refreshments at 3:30 pm, Lecture begins at 4:00pm
|Abstract||Recent advances in VLSI technology are resulting in ever more complex system-on-a-chip designs. Reduced time-to-market and low product cost requirements have been placing increased pressure upon designers to shift as much as possible of the system functionality onto a set of available microprocessor cores so as to reduce the hardware cost of the system and achieve faster time-to-market. Yet one of the fundamental difficulties in implementing larger parts of SOC functionality in software is the stringent timing constraints of the critical modules; methods need to be developed for matching such stringent constraints if embedded processor cores are to be widely used. Low-cost, application-specific microarchitecture customizations promise to be an efficient solution to this problem. The basic advantage of microprocessor cores versus ASICs is the intrinsic reconfiguration capability of the processor by means of software. In order to preserve this fundamental advantage, application-specific features added to the microarchitecture need to be implemented as reprogrammable hardware. Post-manufacturing customization capability can thus provide seamless migration to new applications possibly due to late specification changes or market requirements, while delivering superior levels of performance. In this talk, we outline the incorporation of application specific properties into the processor microarchitecture, thus increasing performance and reducing power consumption. The fundamental approach is the identification of application properties during compile time and their dynamic exploitation during program execution by the processor. The basic characteristic of these properties is that their existence can be statically identifiable by the compiler, and that they can lead to significant improvements in performance when exploiting their behavior dynamically. Such properties may consist of the control structure of the algorithm, the run-time data values and the code manipulating some data structures; for example, an array access, its stride, or its control structure. Microarchitectural features that can be enhanced with such application-specific information include the branch predictor, the cache subsystem, and the processor communication infrastructure; techniques aimed at all three are outlined in this talk.
Alex Orailoglu received his BS Degree cum laude from Harvard University in Applied Mathematics and his M.S. and Ph.D. degrees in Computer Science from the University of Illinois , Urbana-Champaign. Alex Orailoglu is currently a Professor of Computer Science and Engineering at the University of California , San Diego . His research interests include Embedded Systems and Processors, digital and analog test, fault tolerant computing, Computer-Aided Design, and nanoelectronics.