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Cache Power-Performance Optimization

December 2, 2005 @ 3:00 pm - 4:00 pm PST

Cache Power-Performance Optimization

by Dan Nicolaescu

The speed gap between the memory and processor continues to increase. As a consequence the cache system becomes more and more important for bridging this speed gap in order to obtain good performance. As the cache size and associativity increase, its energy consumption becomes a higher part of the total processor energy budget. The high energy consumption is a major problem for current processors, and given the predictions for the semiconductor industry, it will further increase in the future. The traditional way of reducing energy consumption through decreasing the feature size is running out of steam. Therefore solutions need to be found at other levels in the design hierarchy. This dissertation studies the performance and energy consumption of the cache system and proposes and proves effective low complexity, yet highly effective solutions for reducing the cache energy consumption and increasing the processor performance at the architectural level.

The cache energy consumption can be reduced by reducing the number of cache accesses. This can be achieved by using a new architectural component called Cached Load/Store Queue which also allows for a performance improvement by reducing average cache access latency. The energy consumption of highly associative CAM based caches can be improved by using a predictor and changing the way the access is performed. The Way Cache is a novel component that can be used to improve the dynamic and static energy consumption of associative caches by reducing the number of tag and data ways accessed for each cache access.


December 2, 2005
3:00 pm - 4:00 pm PST
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