“Application Mapping Methodologies for NoC-Based MPSOCs”

Title: “Application Mapping Methodologies for NoC-Based MPSOCs”
Speaker: Jürgen Teich, Friedrich-Alexander Universität Erlangen-Nürnberg (FAU)

Date and Time: Tuesday, November 14, 2017 at 3:00PM-4:00PM

Location: DBH 4011

Abstract: 

In this talk, we give an overview of novel techniques for systematically mapping applications to NoC-based multi-core architectures
(MPSoCs). Complex applications requiring heterogenous processing resources are often described by task graphs
with data dependencies. Here, the nodes represent actors or tasks which are typically activated periodically based on the
availability of data. One prominent domain of applications fitting this model is stream processing. Here, it is often important to guarantee
either bandwidth or execution time requirements. But more recently, also security, energy and reliability aspects impose
constraints on the mapping of the tasks as well as their communication to cores, respectively routes in the underlying NoC.

Concerning mapping methodologies, we first present a class of algorithms that perform “Self-Embedding”. The idea is here that
a source node issues a request to find appropriate resources to embed its sucessor tasks, and so on.
The next class of techniques introduced is called “Hybrid Application Mapping (HAM)”. Here, a careful analysis and
characterization of symmetric mappings by constellations of cores and routes is explored in a static (compile-time)
phase called “Design Space Exploration (DSE)”. At run-time, the operating system then only needs to search within such
pre-analysed constellations for finding a concrete mapping that will satisfy the given non-functional constraints by construction.
We present ideas of how timing constraints may be statically analysed in case of compositional MPSoC architectures such that
deadlines or throughput requirements will be automatically met for streaming applications.
Finally, we conclude with a discussion on resource constellations that may satisfy certain security requirements on an MPSoC.

Biography:

Jürgen Teich is with Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany, where he is directing
the Chair for Hardware/Software Co-Design since 2003. He received the M.S. degree (Dipl.-Ing.; with honors)
from the University of Kaiserslautern, Germany in 1989 and the Ph.D. degree (Dr.-Ing.; summa cum laude)
from the University of Saarland, Saarbruecken, Germany, in 1993. In 1994, he joined the DSP design group of Prof. E. A. Lee
in the Department of Electrical Engineering and Computer Sciences (EECS), University of California at
Berkeley (PostDoc). From 1995 to 1998, he held a position at the Institute of Computer Engineering and
Communications Networks Laboratory (TIK), ETH Zurich, Switzerland with his Habilitation
on the topic of `Synthesis and Optimization of Digital Hardware/Software Systems’ in 1996.
From 1998 to 2002, he was Full Professor in the Electrical Engineering and Information Technology
Department, University of Paderborn, Germany.

His current research focuses on electronic design automation of embedded systems
with emphasis on hardware/software co-design, reconfigurable computing and multi-core systems.
Prof. Teich has organized various ACM/IEEE conferences/symposia as Program Chair
including CODES+ISSS´07, FPL´08, ASAP´10, and DATE´2016.
He serves regularly as a TPC member of many program committees including DAC, ASP-DAC, ICCAD, FPL,
ASAP, FPT, FPGA, RECONFIG, ESTIMEDIA, VLSI Design, GECCO, EMO, RTSS, etc.
He also serves in the editorial board of journals including ACM TODAES, IEEE Design and Test and JES and has
edited two text books on Hardware/Software Co-Design and recently a Handbook on this topic (Springer).

Prof. Teich is involved in many interdisciplinary projects on basic research as well as industrial projects.
From 2003-2009, he was an elected board member (Fachkollegiat) of the Deutsche Forschungsgemeinschaft (DFG)
for the area of Computer Architecture and Embedded Systems. He has been the initiator and
coordinator of the DFG priority programme 1148 on “Reconfigurable Computing”.
Since 2010, he has also been the principal coordinator of the Transregional
Research Center 89 “Invasive Computing” funded by the German Research Foundation (DFG).
In 2011, he was elected member of the Academia Europaea.