Date and Time: Monday, July 31, 2017 at 2:00PM-3:00PM
Location: DBH 3011
Abstract: Multicore technology plays a pivotal role in conquering key societal challenges. For example, safe, ecological mobility, wide-spread rollout of eHealth, smart industrial automation and the development of a secure, high-bandwidth, low-latency mobile communication infrastructure for Industry 4.0, all these application domains are critically dependent on high-performance, low power and dependable computing. However, multicore technology also comes with a number of unique challenges for industry and academia. Today, the efficient utilization of massively parallel computing resources largely depends on the experience of individual programmers.
Application-specific accelerators and generic enablement building blocks for Multicore System on Chip (MCSoC) platforms are research foci at the Chair for Integrated Systems at TU München. These building blocks support a more performant, energy efficient, easier to use and more resilient deployment of multicore processors by application programmers and system integrators. In my talk, I will present current and past research projects on wire-speed traffic distribution among Software Defined Networking (SDN) nodes, interconnect virtualization for Network on Chip and processing node resilience, efficient multicore deployment in legacy automotive CAN networks and on-chip diagnosis for effective software debugging.
Biography: Andreas Herkersdorf is a professor at the Department of Electrical and Computer Engineering and also adjunct to the Department of Informatics at Technische Universität München (TUM). He received the diploma degree from TUM in 1987 and the Dr. degree from ETH Zurich, Switzerland, in 1991, both in electrical engineering. Between 1988 and 2003, he has been a research staff member and manager at the IBM Zurich Research Laboratory in Rüschlikon, Switzerland.
Since 2003, Dr. Herkersdorf is head of the Chair for Integrated Systems at TUM. He is a senior member of the IEEE, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer, Elsevier and deGruyter journals for design automation, communications electronics and information technology. His research interests include application-specific multi-processor architectures, IP network processing, Network on Chip, system level SoC modeling and design space exploration methods, and self-aware fault-tolerant computing.