A Pareto-Optimal Compiler for Mapping Task Graphs to Truly Scalable Grids of Processing Cells

Name: Yutong Wang

Chair: Prof. Rainer Doemer

Date: March 2, 2026

Time: 1:00 PM

Location: EH 3206

Committee: Prof. Brian Demsky, Prof. Zhou Li

Title: A Pareto-Optimal Compiler for Mapping Task Graphs to Truly Scalable Grids of Processing Cells

Abstract: Programming scalable system-on-chip architectures composed of processor arrays remains challenging due to the complexity of partitioning applications, assigning tasks and data, and realizing communication under strict locality constraints. Regular grid-based architectures offer scalability and predictable communication, yet mapping real applications onto such platforms is often manual, error-prone, and difficult to validate. This dissertation presents the Grid of Processing Cells Compiler (GPCC), an automated framework that maps application task graphs extracted from C++ specifications onto a truly scalable two-dimensional grid of processing cells with local memories and neighbor-only communication. GPCC automatically analyzes application graphs, performs task and data partitioning, places tasks onto grid locations, and generates consistent on-chip and off-chip communication, producing executable SystemC TLM-2.0 architecture models for system-level simulation and evaluation. GPCC employs a two-level mapping strategy in which tasks are first placed onto processing cells using a dependency-aware recursive search, followed by assignment of communication channels and external I/O resources. In addition, this work introduces an automated design space exploration method that evaluates candidate grid dimensions and identifies Pareto-optimal configurations. Experimental results on embedded applications and synthetic benchmarks demonstrate that GPCC efficiently produces correct executable models, enables systematic exploration of grid-based architectures, and determines suitable grid dimensions with minimal manual effort.

Bio: Yutong Wang is a Ph.D. candidate in Computer Engineering at UC Irvine, working in scalable system-on-chip architectures and SystemC-based modeling. His research centers on automated mapping and design space exploration for grid-based processor arrays through the Grid of Processing Cells Compiler (GPCC).