Title: “A Compiler Infrastructure for Static and Hybrid Analysis of Discrete Event System Models”
Speaker: Tim Schmidt, University of California, Irvine
Date and Time: Friday, April 20, 2018 at 10:00AM-11:00PM
Location: Engineering Hall 3206
Committee: Professor Rainer Doemer (Chair), Fadi Kurdahi, Kwei-Jay Lin
The design of embedded systems is a well-established research domain for many decades. However, the constantly increasing complexity and requirements of state-of-the-art embed- ded systems pushes designers to new challenges while maintaining established design methodologies. Embedded system design uses the concept of Discrete Event Simulation (DES) to prototype and test the interaction of individual components.
In this dissertation, we provide the Recoding Infrastructure for SystemC (RISC) compiler framework to perform static and hybrid analysis of IEEE SystemC models. On one hand, RISC generates thread communication charts to visualize the communication between individual design components. The
visualization respects the underlying discrete event simulation semantics and illustrates the individual synchronization steps. On the other hand, RISC translates a sequential model into a parallel model
which effectively utilizes multi- and many-core host simulation platforms for faster simulation. This work extends the conflict analysis capabilities for libraries, dynamic memory allocation, channel instance awareness, and references. Additionally, the traditional thread level parallelism is extended with data level parallelism for even faster simulation.