CECS Seminar Series

Title: “Optimizing private local memories in heterogeneous architectures”

Speaker: Christian Pilato, Università della Svizzera italiana (USI), Lugano, Switzerland

Date and Time: Wednesday, June 14, 2017 at 11:00AM-12:00PM

Location: ICS 432




Modern Systems-on-Chip (SoC) architectures and state-of-the-art computing platforms that integrate CPUs with FPGAs are heterogeneous systems featuring an increasing number of hardware accelerators. Private local memories play a key role in the design of these components both with respect to performance optimization and because they are responsible for most of their area and power dissipation. Each local memory unit is usually implemented with a multibank microarchitecture based on the combined requirements of each hardware block accessing the corresponding data. However, the creation of these multibank memory microarchitectures is not well supported by current design flows, and the designers must perform this tedious and error-prone process manually.

In this talk, I will present a system-level methodology for the generation of multi-bank memories in heterogeneous architectures. The methodology is supported by Mnemosyne, an open-source prototype CAD tool that can be easily integrated into commercial design flows. Mnemosyneincludes various technology-aware optimizations to reduce the memory cost (area and power) by efficiently reusing the physical banks for storing different data. With Mnemosyne,we can reduce the memory cost of single accelerators by up to 45%. Moreover, when reusing memory IPs across accelerators, we achieve area savings that range between 17% and 55% compared to the case where the memory elements are designed separately.


Christian Pilato is a Postdoctoral Researcher at the ALaRi institute of Università della Svizzera italiana (USI), Lugano, Switzerland. He received the Laurea degree in computer engineering and the Ph.D. degree in information technology from Politecnico di Milano, Italy, in 2007 and 2011, respectively. From 2013 to 2016, he was a Postdoctoral Research Scientist with the Department of Computer Science, Columbia University, USA. He has been visiting researcher at NanGate, Chalmers University of Technology, and Delft University of Technology. 
His current research interests include high-level synthesis, reconfigurable systems and system-on-chip architectures, with emphasis on memory aspects. He has actively participated in several projects sponsored by the European Union and DARPA, as well as a research center supported by SRC. Dr. Pilato served as the Program Chair of the Embedded and Ubiquitous Conference (EUC) in 2014. He is currently involved in the program committees of many conferences on embedded systems, CAD, and reconfigurable architectures, such as FPL, DATE, and CASES. He is a Member of IEEE and ACM.