RISC Compiler and Simulator, Beta Release V0.3.0:Out-of-Order Parallel Simulatable SystemC Subset

Guantao Liu, Tim Schmidt, and Rainer Dömer, “RISC Compiler and Simulator, Beta Release V0.3.0:Out-of-Order Parallel Simulatable SystemC Subset” CECS TR 16-06, posted on September 30, 2016