Modeling and Evaluation of a Cache-less Grid of Processing Cells

Name: Vivek Govindasamy

Chair: Prof. Rainer Doemer

Date: March 11, 2025

Time: 10:00 AM

Location: EH 3206 (CECS Conference Room)

Committee: Prof. Mohammad Al Faruque, Prof. Ian Harris

Title: Modeling and Evaluation of a Cache-less Grid of Processing Cells

Abstract: Modern processors experience memory contention when the speed of their computational units exceeds the rate at which new data is available to be processed. This phenomenon is well known as the memory wall and is a great challenge in computer engineering. The reason for this phenomenon is the unequal growth rate in memory access speeds compared to processor clock rates. In order to mitigate the memory bottleneck in classic computer architectures, a scalable parallel computing platform called the Grid of Processing Cells (GPC) has been proposed. To evaluate its effectiveness, we model the GPC in this work at the instruction-level and functional-level using SystemC TLM-2.0, with a focus on memory contention. In an advanced model, individual GPC cells can be switched as needed between the two abstraction levels. We then show that our mixed-level system model enables fast and accurate simulations. We test multiple streaming applications on the GPC, analyze software-based optimization methods and their effects on the GPC, at both abstraction levels. The performance is then compared against the traditional shared memory processor (SMP) architecture. Finally, experimental results show improved execution times on the GPC primarily due to a large decrease in main memory contention.

Short Bio: Vivek Govindasamy received his Bachelor of Technology degree in Electrical Engineering from Vellore Institute of Technology, India in 2020, and M.S. degree in Computer Engineering from the University of California Irvine, Irvine, CA, USA in 2022. He is currently pursuing his PhD degree in Computer Engineering under the supervision of Professor Rainer Doemer. His research is focused on modeling and simulation of many-core computer architectures.