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High Level Systems Validation Using Hierarchical Message Sequence Charts

Name: High Level Systems Validation Using Hierarchical Message Sequence Charts
Start: 2007-04-26T15:00:00-07:00
End: 2007-04-26T16:00:00-07:00

April 26, 2007 @ 3:00 pm - 4:00 pm PDT

Dr. Praveen Murthy, Fujitsu Labs of AmericaCalit2 Auditorium, University of California, Irvine
April 26, 2007
Abstract

Details

Date: April 26, 2007
Time:
3:00 pm - 4:00 pm PDT
Event Category: Seminars at CECS