Conference Proceedings

International Conference on High Performance Computing in Asia Pacific Region (HPC Asia)

Location: Beijing, China
Web Site:http://www.ict.ac.cn/hpcasia2005/

P.D’Alberto and A. Nicolau, “Adaptive Strassen and ATLAS’s DGEMM: A Fast Square-Matrix Multiply for Modern High-Performance Systems,” International Conference on High Performance Computing in Asia Pacific Region (HPC Asia), November 30-December 3, 2005. download pdf

 

IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

Location: Napa, CA
Web Site: http://www.fccm.org/

S. Banerjee, E. Bozorgzadeh, and N. Dutt, “Considering runtime reconfiguration overhead in Task Graph Transformations for dynamically reconfigurable architectures,” IEEE symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005.

 

IEEE International Conference on Sensor and Ad Hoc Communications and Networks(SECON)

Location: Santa Clara, CA
Web Site: http://www.ieee-secon.org/2005/home.html

C.Park, K. Lahiri, and A. Raghunathan, “Battery Discharge Characteristics of Wireless Sensor Nodes: An Experimental Analysis ,” IEEE International Conference on Sensor and Ad Hoc Communications and Networks(SECON),September 26-29, 2005.

 

International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004)

Location: Stockholm, Sweden
Web Site: http://www.codes-isss.org/

S. Banerjee and N. Dutt, “Efficient Search Space Exploration for HW-SW Partitioning,” CODES+ISSS 2004, Stockholm, Sweden, pp 122-127, September 8-10, 2004 download pdf

M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, ” Analytical Models for Leakage Power Estimation of Memory Array Structures,” CODES+ISSS 2004,”Stockholm, Sweden, pp 146-151, September 8-10, 2004 download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based On-chip Communication Architectures,” CODES+ISSS 2004, Stockholm, Sweden, pp 242-247, September 8-10, 2004 download pdf

F. Rivera, M. Sanchez-Elez, M. Fernandez, R. Hermida, and N. Bagherzadeh, “Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures,” CODES+ISSS 2004, Stockholm, Sweden, pp 30-35, September 8-10, 2004 download pdf

A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau, “Operation Tables for Scheduling in the Presence of Incomplete Bypassing,” CODES+ISSS 2004, Stockholm, Sweden, pp 194-199, September 8-10, 2004 download pdf

 

ACM/IEEE International Conference on Computer-Aided Design

Location: San Jose, CA
Web Site: http://www.iccad.com/

S. Ghiasi, S. Choudhuri, E. Bozorgzadeh, M. Sarrafzadeh, “A Unified Theory for Timing Budget Management,” ACM/IEEE International Conference on Computer-Aided Design, November 2004. download pdf

 

Design, Automation and Test in Europe Conference (DATE ‘04)

Location: Paris, France
Web Site: http://www.date-conference.com/

J. Aragon, D. Nicolaescu, A. Veidenbaum, and A. Badulescu, “Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1374-1375, February 16-20, 2004

B. Arslan and A. Orailoglu, “Circular-Scan: A Scan Architecture for Test Cost Reduction,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1290-1295, February 16-20, 2004

N. Bansal, S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 474-479, February 16-20, 2004

A. Gordon-Ross, F. Vahid, and N. Dutt, “Automatic Tuning of Two-Level Caches to Embedded Applications,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 208-213, February 16-20, 2004

S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 114-120, February 16-20, 2004

M. Heath, W. Burleson, and I. G. Harris, “Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC,” IEEE/ACM Design Automation and Test in Europe Conference (DATE ’04), Paris, France, February 16-20, 2004 download pdf

R. Lysecky, and F. Vahid, “A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 480-485, February 16-20, 2004

P. Mishra, N. Dutt, “Graph-Based Functional Test Program Generation for Pipelined Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 182-187, February 16-20, 2004

A. Nacul and T. Givargas, “Dynamic Voltage and Cache Reconfiguration for Low Power,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1376-1378, February 16-20, 2004

O. Sinanoglu and A. Orailoglu, “Scan Power Minimization Through Stimulus and Response Transformations,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 404-409, February 16-20, 2004

C. Zhang and F. Vahid, “Using a Victim Buffer in an Application-Specific Memory Hierarchy,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 220-227, February 16-20, 2004

C. Zhang, F. Vahid, and R. Lysecky, “A Self-Tuning Cache Architecture for Embedded Systems,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 142-147, February 16-20, 2004

C. Zhang, J. Yang, and F. Vahid, “Low Static-Power Frequent-Value Data Caches,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 214-219, February 16-20, 2004

 

Asia South Pacific Design Automation Conference 2004 Pacifico Yokohama (ASP-DAC 2004)

Location: Yokohama, Japan
Web Site: http://www.aspdac.com/

S. Abdi and D. Gajski, “On Deriving Equivalent Architecture Model from System Specification,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 322-327, January 27-30, 2004

L. Cai, H. Yu and D. Gajski, “A Novel Memory Size Model for Variable-Mapping in System Level Design,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 813-818, January 27-30, 2004

B. Gorji-Ara, P. Chou, N. Bagherzadeh, M. Reshadi and D. Jensen, “Fast and Efficient Voltage Scheduling by Evolutionary Slack Distribution,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 659-662, January 27-30, 2004

P. Heydari, “High-Frequency Noise in RF Active CMOS Mixers,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 57-61, January 27-30, 2004 download pdf

D. Shin, S. Abdi, and D. Gajski, “Automatic Generation of Bus Functional Models from Transaction Level Models,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 756-758, January 27-30, 2004

A. Shrivastava and N. Dutt, “Energy Efficient Code Generation Exploiting Reduced Bit-Width Instruction Set Architectures (rISA),”Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 475-477, January 27-30, 2004

O. Sinanoglu and A. Orailoglu, “Efficient RT-Level Fault Diagnosis Methodology,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 212- 217, January 27-30, 2004

R. Topaloglu and A. Orailoglu, “On Mismatch in the Deep Sub-Micron Era – From Physics to Circuits,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 62-67, January 27-30, 2004

H. Yu, R. Doemer and D. Gajski, “Embedded Software Generation from System-Level Design Languages,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 463-468, January 27-30, 2004

 

IEEE International Symposium on Circuits and Systems (ISCAS 2004)

Location: Vancouver, Canada
Web Site: http://www.iscas2004.org/

A. Yazdi and P. Heydari, “A Novel Non-Uniform Distributed Amplifier,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

A. Safarian and P. Heydari, “Design and and Analysis of a Distributed Regenerative Frequency Divider Using a Distributed Mixer,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

Ravindran Mohanavelu and Payam Heydari, “A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

 

Design Automation Conference 2004 (DAC 2004)

Location: San Diego, CA
Web Site: http://www.dac.com/

S. Abdi and D. Gajski, “Automatic Generation of Equivalent Architecture Model from Functional Specification,” Design and Automation Conference (DAC 2004), pp 608-613, June 7-11, 2004 download pdf

P. Biswas, V. Choudhary, K. Atasu, L. Pozzi, P. Ienne, and N. Dutt, “Introduction of Local Memory Elements in Instruction Set Extensions,” Design and Automation Conference (DAC 2004), pp 729-734, June 7-11, 2004 download pdf
L. Cai, A. Gerstlauer, and D. Gajski, “Retargetable Profiling for Rapid, Early System-Level Design Space Exploration,” Design and Automation Conference (DAC 2004), pp 281-286, June 7-11, 2004

R. Jejurikar, C. Pereira, and R. Gupta, “Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems,” Design and Automation Conference (DAC 2004), pp 275-280, June 7-11, 2004

A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt and R. Gupta, “Proxy-Based Task Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices,” Design and Automation Conference (DAC 2004), pp 556-561, June 7-11, 2004 download pdf

R. Lysecky, F. Vahid, and S. Tan, “Dynamic FPGA Routing for Just-in-Time FPGA Compilation,” Design and Automation Conference (DAC 2004), pp 659-662, June 7-11, 2004 download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration,” Design and Automation Conference (DAC 2004), pp 113-118, June 7-11, 2004 download pdf

 

International Conference on Embedded and Reconfigurable Systems and Architecture

E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, “Incremental Timing Budget Management in Programmable Systems,” International Conference on Embedded and Reconfigurable Systems and Architecture, July 2004. download pdf

 

First Workshop on Embedded Systems for Real-Time Multimedia

S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, and N. Venkatasubramanian, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices,” ESTIMedia 2003, First Workshop on Embedded Systems for Real-Time Multimedia, Newport Beach, CA, October 2003. download pdf

 

IEEE High-Level Design, Validation, and Test Workshop

E. Gaudette, M. Moussa, and I. G. Harris, “A Method for the Evaluation of Behavioral Fault Models,” IEEE High-Level Design, Validation, and Test Workshop (HLDVT), November 2003. download pdf

 

15th IASTED International Conference on Parallel and Distributed Computing and Systems

S. Ghiasi, K. Nguyen, E Bozorgzadeh, and M Sarrafzadeh, “On Computation and Resource Management in Networked Embedded Systems,” International Conference on Parallel and Distributed Computing and Systems, pp 445-451, Marina del Rey, CA, November 3-5, 2003.  download pdf

 

Design, Automation, and Test in Europe Conference (DATE ‘03)

F. Doucet, R. Gupta, and S. Shukla, “Introspection in System-Level Language Frameworks: Meta-Level or Integrated,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 382-387, Munich, Germany, March 2003 download pdf

A. Gerstlauer, H. Yu, and D. Gajski, “RTOS Modeling for System Level Design,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 130-135, Munich, Germany, March 2003 download pdf

A. Ghosh and T. Givargis, “Analytical Design Space Exploration of Caches for Embedded Systems,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 650-655, Munich, Germany, March 2003 download pdf

S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, “Dynamic Conditional Branch Balancing During the High-Level Synthesis of Control-Intensive Designs,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 270-275, Munich, Germany, March 2003 download pdf

M. Mamidipaka and N. Dutt, “On-Chip Stack Based Memory Organization for Low Power Embedded Architectures,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1082-1087, Munich, Germany, March 2003 download pdf

D. Nicolaescu, A. Veidenbaum, and A. Nicolau, “Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1064-1068, Munich, Germany, March 2003 download pdf

C. Pan, N. Bagherzadeh, A. Kamalizad, and A. Koohi, “Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 468-473, Munich, Germany, March 2003 download pdf

P. Petrov and A. Orailoglu, “Power Efficiency Through Application-Specific Instruction Memory Transformations,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 30-35, Munich, Germany, March 2003 download pdf

W. Roa and A. Orailoglu, “Virtual Compression Through Test Vector Switching for Scan Based Design,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 104-109, Munich, Germany, March 2003 download pdf

M. Sánchez-Élez, M. Férnandez, M. Anido, H. Du, N. Bagherzadeh, and R. Hermida, “Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 36-41, Munich, Germany, March 2003
download pdf

Z. Zeng, Q. Zhang, I. G. Harris, and M. Ciesielski, “Fast Computation of Data Correlation Using BDDs,” IEEE/ACM Design Automation and Test in Europe Conference (DATE ’03), Munich, Germany, March 2003 download pdf

 

4th Workshop on Microprocessor Test and Verification

P. Mishra and N. Dutt, “A Methodology for Validation of Microprocessors using Equivalence Checking Communication Refinement for System Level Design,” 4th Workshop on Microprocessor Test and Verification, Austin, TX, May 2003