Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement

by Aseem Gupta

Location: DBH 3011

Date and Time: May 29, 2009 1:30pm

Committee:
Chancellor’s Professor Nikil Dutt (Chair)
Professor Fadi Kurdahi
Professor Tony Givargis

Abstract:
Process scaling and shrinking device geometries have resulted in chips with greater performance and complexity levels. However, these advancements have come at the cost of higher power densities and increased operating temperatures. The inability to control the operating temperatures by existing cooling techniques is the principal reason for discontinuation of an increase in frequencies and introduction of multi-core architectures. Apart from operability, high temperatures have unfavorable consequences such as: increased leakage power, reduced interconnect life time, slowing of interconnects and transistors, need for expensive package and cooling mechanisms, and increased manufacturing cost and design effort. Traditionally, thermal issues have been examined only at the post-synthesis stages of the design flow. This thesis attempts to migrate the “thermal awareness” from the physical level design phase to early stages of the VLSI design flow and utilize it to target various design metrics such as power, performance, reliability, and operability. This thesis advances the procedure of leakage power estimation by coupling it with thermal profile estimation and capturing the positive interdependence between temperature and leakage power. It also advances the traditional role of communication architecture to that of an active thermal manager. The proposed communication architecture based thermal manager delays the execution of chosen components by regulating the flow of data over the on-chip communication fabric. This dissertation demonstrates the need of examining the effects of frequency, supply voltage, power dissipation, and temperature on SRAM reliability in a mutually interrelated manner. Our observation contradicts the conventional belief that increasing supply voltage always reduces the failure rate in SRAMs. Because of thermal effects, an increase in the supply voltage can also lead to increase in the SRAM failure rate. This thesis also extends the procedure of system level floorplanning to manage the leakage power and reliability of the design. The fundamental contribution of this thesis is that it advances the traditional design flow in the direction of incorporating thermal awareness during various stages of the flow.