Programming FPGA in C using ROCCC
| Presenters | Jason Villarreal, Adrian Park, Roby Atadero, and Walid Najjar | |||
| CECS Host | Professor Fadi Kurdahi | |||
| Location | CALit2 3008, University of California, Irvine | |||
| Date & Time | October 6, 2010 Light refreshments at 9:30am, Tutorial begins 10:00am |
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| Abstract | ROCCC (Riverside Optimizing Compiler for Configurable Computing) is a C to VHDL compilation framework specifically focused on FPGA-based code acceleration. Its focus is on compile time transformations and optimizations aimed at generating an efficient circuit from a loop nest. Its objectives are to maximize parallelism within the constraints of the target device, optimize clock cycle time by efficient pipelining and minimize the area utilized. Furthermore, ROCCC relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory. ROCCC 2.0 is a free and open source tool that supports a modular bottom-up approach to the programming of FPGA accelerators, supporting code reuse at multiple levels while maintaining full compatibility with C. It has been ported to several platforms including Xilinx development boards and the Convey Computers HC-1. |