NEC’s Manycore Platforms for Low-Power Embedded System

Speaker Naoki Nishi
GM, NEC Central Research Labs,
Japan
CECS Host Professor Nikil Dutt
Location Donald Bren Hall (DBH) 3011, University of California, Irvine
Date & Time November 12, 2009
Refreshments at 1:30pm; Talk begins 2:00pm
Abstract After short introduction of NEC’s R&D vision related to future ICT system handling real world in real time, two examples of NEC’s manycore research activities will be presented. First example is an in-vehicle vision processor IMAPCAR-2 which supports SIMD-MIMD morphing, and the second is a fine grain manycore architecture called STP (Stream TransPoser) engine which is a kind of dynamically reconfigurable hardware with C level language SDK support.
Biography Naoki Nishi is a general manager at central research labs., NEC. He jointed NEC in 1984, where he worked in research on micro-architectures and LSI development of the NEC SX vector supercomputer, After the development of CMOS vector supercomputer SX-4 in 1996, he has been conducting research on high-performance, low-power multi-/many-cores. Naoki Nishi received his B.E. and M.E. degrees in system engineering from Hiroshima University, Japan.