Compiler-in-the-Loop Exploration of Programmable Embedded Systems

by Aviral Shrivastava

Embedded Systems are characterized by strict, multi-dimensional design constraints such as power, performance, and time-to-market. Increasingly, embedded processors are being employed for the flexibility of programmable solutions for embedded systems. However, in order to satisfy all the design constraints simultaneously, such embedded processors use many idiosyncratic architectural features (e.g., partial register renaming and partial bypassing), which in turn complicates the task of efficient software generation for the embedded processors.

The challenge in developing compilers for embedded processors is not only in developing compiler technology to exploit the idiosyncratic design feature, but also to perofrm the required analysis in the limited resources present in embedded systems. When the compiler is able to exploit the idiosyncratic design feature, it often has significant impact on the overall system characteristics. In such cases, the compiler effects cannot be ignored while searching for the optimal processor design. Traditionally exploration to find an optimal processor is performed by simulating the same application binary over different processor variations. The variation that faresbest on the cost metric is chosen. Compiler effects in such an exploration scheme are typically accounted for, using ad-hoc methods, like hand-tuning the application binary, or scaling the simluation results. Such ad-hoc methods miss many interesting design options, and may even result in incorrect decisions being made during architectural exploration.

My thesis proposes a Compiler-in-the-Loop (CIL) Design Space Exploration (DSE) methodology to systematically include compiler effects in the search for an optimal embedded processor. In this talk I will demonstrate the need and usefulness of CIL DSE at several levels of design abstractions: the micro-architectural level, the architectural level, memory level, and at the processor-memory-interface level. The CIL DSE approach results in a more meaningful exploration of the design space, and allows embedded system designers to efficiently evaluate architectural options with respect to system constraints quickly, reliably and early in the design process.