Challenges in Compiling for Modern Architectures

Speaker Dr. Bilha Mendelson
IBM Haifa Research Lab
Location IERF 144/148
Date & Time April 27 , 2006
Refreshments at 10:30am, followed by Lecture
Abstract In the last two decades the computer architecture performance was relaying on frequency. However, as the frequency race seems to reach its physical limitations, the real challenge is how to keep on improving the performance in respect to the “Moore’s Law.” New architectural ideas are introduced, such as the use of multi-threading, multi cores architectures including homogeneous and heterogeneous ones (like the Cell processor). 

What does this mean for their usability? How this influence the software development cycle? What kind of challenges they impose on compilers? In the talk I will address these issues and discuss some new research directions.

Biography Bilha Mendelson is a manager of the Code Optimization Technology department in the IBM Haifa Research Lab, Israel. Since joining IBM in 1990, she has been developing optimizations for DSP compiler and for the AS/400 optimizing translator. She received a B.Sc. and an M.Sc. in Computer Science from the Technion, Israel Institute of Technology, and a Ph.D. in Computer Engineering from the University of Massachusetts at Amherst. She also received an MBA from the Haifa University in Israel. She holds several patents primarily in the area of code optimization. Her areas of interest include code optimization algorithms, compiler technology, computer architecture, and performance improvement issues.