Beyond Memory Cells for Leakage and Temperature Control in SRAM-based Units, the Peripheral Circuits Story

by Houman Homayoun

Location: Bren Hall 4011

Date and Time: September 3, 2011 2:30pm

Professor Fadi Kurdahi (Chair)
Professor Alex Veidenbaum,
Professor Jean-Luc Gaudiot,
Professor Alex Nicolau.

Leakage currents in on-chip SRAMs: caches, branch predictor, register files and TLBs, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines, making remaining SRAM components, in particular large drivers, the primary source of leakage. We proposes an integrated circuit and architectural approach to reduce this source of leakage in all major SRAM-based units of the processor, controlling them in a uniform way, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Various low-power modes are defined, from basic to ultra-low power, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to be significant for all SRAM units. Resulting temperature reduction, including the effect of positive feedback between temperature and leakage power, is evaluated. A significant temperature reduction is achieved in each unit.