Index of /~cad/publications/SpecC/2003

Name	Last modified	Size

Parent Directory		-
TR-03-02.methodology..>	2003-03-11 03:26	1.3M
TR-03-03.channel.pdf	2003-03-11 03:26	183K
TR-03-06.verificatio..>	2003-03-11 03:26	125K
TR-03-08.communicati..>	2003-03-11 03:26	135K
TR-03-10.tlm.pdf	2003-09-18 11:37	255K
TR-03-11.systemc.pdf	2003-09-18 11:37	316K
TR-03-12.RTOS.pdf	2003-09-18 11:37	104K
TR-03-13.c2sc.pdf	2003-09-18 11:37	382K
TR-03-29.arproof.pdf	2003-10-01 13:21	116K
TR-03-30.comm.pdf	2003-10-16 18:01	446K
TR-03-30.comm.ps.gz	2003-10-16 18:01	503K
TR-03-33.cr.pdf	2003-11-19 00:02	97K
TR-03-41.tutorial.pdf	2004-01-05 15:31	5.4M
TR-03-42.RTL.pdf	2004-01-30 06:33	303K
codes03.RTOS.pdf	2004-03-19 15:03	145K
codes03.tlm.pdf	2004-03-19 15:15	130K
dac03.sccr.pdf	2003-10-23 17:05	479K
date03.RTOS.pdf	2003-03-11 02:51	61K
date03.RTOS.ps.gz	2003-03-11 02:51	257K

UCI Cadlab

SpecC Publications

This directory contains UCI Cadlab publications related to the SpecC system-level design environment for the year 2003.

Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski, "RTOS Modeling for System-Level Design," Proceedings of Design, Automation & Test in Europe, Munich, Germany, March 2003.
Samar Abdi, Dongwan Shin, Daniel D. Gajski, "Automatic Communication Refinement for System Level Design," Proceedings of Design Automation Conference, Anaheim, CA, June 2003.
Lucai Cai and Daniel Gajski, "Transaction Level Modeling: An Overview," Proceedings of the International Conference on Hardware/Software Codesign & System Synthesis, Newport Beach, CA, October 2003.
Haobo Yu, Andreas Gerstlauer, Daniel Gajski, "RTOS Scheduling in Transaction Level Models," Proceedings of the International Conference on Hardware/Software Codesign & System Synthesis, Newport Beach, CA, October 2003.
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski, "C-based Interactive RTL Design Methodology," CECS, UC Irvine, Technical Report CECS-TR-03-42, December 2003.
Samar Abdi, Junyu Peng, Haobo Yu, Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Tutorial," CECS, UC Irvine, Technical Report CECS-TR-03-41, July 2003.
Dongwan Shin, Samar Abdi, Daniel Gajski, "Automatic Generation of Bus Functional Models from Transaction Level Models," CECS, UC Irvine, Technical Report CECS-TR-03-33, November 2003.
Andreas Gerstlauer, "Communication Abstractions for System-Level Design and Synthesis," CECS, UC Irvine, Technical Report CECS-TR-03-30, October 2003.
Samar Abdi and Daniel D. Gajski, "Provably Correct Architecture Refinement," CECS, UC Irvine, Technical Report CECS-TR-03-29, September 2003.
Kiran Ramineni and Daniel Gajski, "C to SpecC Conversion Style," CECS, UC Irvine, Technical Report CECS-TR-03-13, April 2003.
Haobo Yu, Andreas Gerstlauer, Daniel Gajski, "RTOS Scheduling in Transaction Level Models," CECS, UC Irvine, Technical Report CECS-TR-03-12, March 2003.
Lucai Cai, Shireesh Verma, Daniel D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," CECS, UC Irvine, Technical Report CECS-TR-03-11, May 2003.
Lucai Cai and Daniel Gajski, "Transaction Level Modeling in System," CECS, UC Irvine, Technical Report CECS-TR-03-10, March 2003.
Samar Abdi and Daniel Gajski, "Automatic Communication Refinement for System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-08, March 2003.
Samar Abdi and Daniel Gajski, "Formal Verification of Specification Partitioning," CECS, UC Irvine, Technical Report CECS-TR-03-06, March 2003.
Lukai Cai and Daniel Gajski, "Channel Mapping in System Level Design," CECS, UC Irvine, Technical Report CECS-TR-03-03, January 2003.
Daniel Gajski, Junyu Peng, Andreas Gerstlauer, Haobo Yu, Dongwan Shin, "System Design Methodology and Tools," CECS, UC Irvine, Technical Report CECS-TR-03-02, January 2003.

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