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Results for MP3 decoder design with ESE demonstrate the advantages of ESE over traditional manual RTL level design.

Fast and accurate ESE TLMs

Time and accuracy trade-off
Time and accuracy trade-off among different models.

The plot above compares TLMs and Board models generated by ESE with traditional Pin/Cycle Accurate RTL Models (PCAMs) and Instruction-Set Models (ISMs) for an MP3 decoder design. PCAMs and ISMs take several hours to simulate with mixed results in accuracy. The timed TLMs generated by ESE provide accuracy in estimation within 8% of board prototype. TLMs are also applicable to any type or complexity of design as opposed to ISMs. Therefore using TLMs generated automatically by ESE, system designers can evaluate design decisions in a matter of seconds instead of waiting for hours or even days for a cycle accurate simulation to complete. Thus, the design modification and evaluation cycle is shortened, leading to significantly more opportunities for design optimization.

ESE Design Quality

Manual vs ESE
Comparison of manual and ESE generated designs.

The above plots compare performance and area of manual and ESE generated designs for MP3 decoder implemented on 4 platforms. SW+0 refers to a purely software implementation where all reference C code for MP3 decoder mapped to Microblaze processor. SW+1 is the design with one DCT implemented in custom HW with remaining MP3 code on Microblaze. SW+2 implements both left and right channel DCTs in HW. Finally SW+4 implements both left and right channel DCTs and IMDCTs in custom HW. The above chart shows the number of FPGA slices and BRAMs needed to implement the 4 designs. It also plots the time to decode 1 frame of MP3 data by each design. It can be seen that as more HW components are added, the area increases while decoding time comes down. By adding HW DCTs we get SW+1 and SW+2, which increase the design cost, but give only marginal improvements in performance. Once the IMDCTs are also moved to HW, we get SW+4 which has the highest area, using almost all the available slices on the FPGA. However, it gives the best performance of all the designs, with more than twice the decoding speed as the pure SW implementation.

The same partitioning and platform as manual MP3 designs was used to implement MP3 decoder with ESE. It can be seen that ESE designs use more BRAMs but fewer FPGA slices than manual design. This is because the ESE generated HW components used more memory intensive controllers than the manual designs. The execution speed of ESE designs were comparable to manual design. Therefore, ESE can automatically generate prototypes for multi-core platforms with the same quality as manual design.

Design Time Savings with ESE

Manual vs ESE
Design time savings with ESE.

Traditional design practice starts with RTL and embedded SW coding for selected platforms. The reference C specification model is used for developing test bench to verify the cycle accurate models. For MP3 platforms with HW components, the RTL development time was in the order of months. As a result, board prototypes for these designs took between 40 to 60 days. ESE drastically cuts prototype development time by automatically generating TLM and RTL models. With ESE, the final board prototypes for MP3 designs were available in less than a week after the specification model was finalized. Consequently, ESE results in significant savings in design cost and shorter development cycles.

Verification Time Savings with ESE

Manual vs ESE
Verification time savings with ESE.

As a consequence of traditional cycle accurate modeling, designers must make design optimizations and changes on RTL and low level SW code. Each change needs to be verified using time consuming cycle accurate simulations. Each cycle accurate simulation cycle took 15 to 18 hours for MP3 designs. This is a significant component of design time. Although at speed on-board verification is faster than even reference C simulation, bugs found in on-board testing are difficult to trace back to RTL.

ESE removes the burden of cycle accurate simulations by moving the design abstraction to TLM. ESE generated TLMs execute at the same speed as reference C simulation. Design changes are made at the transaction level and can hence be verified and debugged using the automatically generated high speed TLMs. TLMs are easier to debug and maintain because their code size is at least an order of magnitude less than RTL.

Automatic RTL generation is also less likely to introduce bugs in the design compared to manual RTL optimizations. This has been true in the past when the modeling abstraction moved from gate level to RTL with the use of logic synthesis tools. Therefore, ESE reduces verification time from an order of several hours or even days to a few seconds. As a results, designers can use ESE to make platform and application optimizations at a higher level, automatically generate TLMs and verify the optimizations in a few seconds.

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