Result-Oriented System-Level Modeling for Efficient Design of Embedded Systems NSF CAREER Award #0747523 Principal Investigator: Rainer Dömer

Abstract Activities Findings Publications

Abstract We are surrounded by embedded computing systems, ranging from video-enabled mobile phones over real-time automotive applications to reliable medical devices. Just as the quality of an architectural blue-print determines the quality of the resulting building, the model of an embedded system is the key to its successful implementation. This project moves research and education on embedded system design forward in the area of system-level specification and modeling. While traditional work largely has focused on simulation and synthesis from a given system model, this project addresses the creation and optimization of system models for effective use in existing design processes. The results of this project are directly applicable to established system design flows in industry and fit well into existing and new courses in computer engineering education. This project optimizes the modeling of embedded systems by use of four novel techniques. First, it advances a new model of computation, named ConcurrenC, which refines the generic capabilities of common C-based system-level description languages. Second, the creation of the system model is automated by computer-aided re-coding that derives an executable model directly from reference code. Third, the efficiency of the model is optimized using Result-Oriented Modeling (ROM), which, in contrast to traditional Transaction-Level Modeling (TLM), offers gains in simulation speed of multiple orders of magnitude and highest accuracy at the same time. Fourth, this project investigates TLM of computation, an area where TLM has not been applied before. This NSF CAREER project has been proven highly successful. Significant results include (A) the study of concurrent models of computation and in particular break-through advances in parallel system simulation, and (B) the development of computer-aided recoding techniques for model optimization and refinement. Activities W. Chen, S. Sun, B. Zhang, R. Dömer: "System Level Modeling of a H.264 Decoder", Center for Embedded Computer Systems, Technical Report 08-10, August 2008. T. Bohr, R. Dömer: "A Flexible Video Stream Converter", Center for Embedded Computer Systems, Technical Report 08-13, October 2008. B. Zhang, R. Dömer: "An Eclipse-based Software Platform for the Recoding Integrated Development Environment (RIDE)", Center for Embedded Computer Systems, Technical Report 09-06, May 2009. K. P. Kim, R. Dömer: "Design Exploration using Multiple ARM Instruction Set Simulators - A Case Study on a JPEG Encoder", Center for Embedded Computer Systems, Technical Report 09-08, May 2009. Y. Guo, R. Dömer: "A Hybrid Instruction Set Simulator for System Level Design", Center for Embedded Computer Systems, Technical Report 10-06, June 2010. X. Han, W. Chen, R. Dömer: "A Parallel Transaction-Level Model of H.264 Video Decoder", Center for Embedded Computer Systems, Technical Report 11-03, June 2011. C. Chang, R. Dömer: "System Level Modeling of a H.264 Video Encoder", Center for Embedded Computer Systems, Technical Report 11-04, June 2011. T. Mathew, R. Dömer: "A Custom Thread Library Built on Native Linux Threads for Faster Embedded System Simulation", Center for Embedded Computer Systems, Technical Report 11-10, December 2011. G. Liu, R. Dömer: "Performance Evaluation and Optimization of A Custom Native Linux Threads Library", Center for Embedded Computer Systems, Technical Report 12-11, October 2012. X. Han, Y. Samei, R. Dömer: "System-Level Modeling and Refinement of a Canny Edge Detector", Center for Embedded Computer Systems, Technical Report 12-13, November 2012. X. Han, R. Dömer: "An Extended Eclipse Platform for Recoding System-Level Models", Center for Embedded Computer Systems, Technical Report 13-04, April 2013. G. Liu, R. Dömer: "A User-level Thread Library Built on Linux Context Functions for Efficient ESL Simulation", Center for Embedded Computer Systems, Technical Report 13-07, June 2013. G. Liu, R. Dömer: "A Hybrid Thread Library for Efficient Electronic System Level Simulation", Center for Embedded Computer Systems, Technical Report 13-11, October 2013. G. Liu, T. Schmidt, R. Dömer, A. Dingankar, D. Kirkpatrick: "Out-of-Order Parallel Simulation of SystemC Models Using Intel(R) MIC Architecture", Presentation at NASCUG Meeting, San Francisco, California, June 2014. Findings The major findings in this project concentrate on (a) ConcurrenC model of computation and (b) Recoding of embedded system models. (a) In the context of ConcurrenC, we have created a novel model of computation which features fast simulation algorithms and parallel, multi-core, and distributed simulators and corresponding compilers. Together, these results contribute to significantly faster validation of embedded systems. (b) In the context of Recoding, we have designed novel methods and tools for computer-aided modeling and transformation of design models. Our experimental results on video codec applications demonstrate feasibility and promise significant reduction in design specification and modeling time. For more details on our findings, please refer to the reports and publications below. W. Chen, R. Dömer: "ConcurrenC: A Novel Model of Computation for Effective Abstraction of C-based SLDLs", Center for Embedded Computer Systems, Technical Report 09-07, May 2009. R. Dömer: "Efficient Modeling of Embedded Systems using Computer-Aided Re-Coding", Invited Tutorial at IESS'09, Langenargen, Germany, Sep. 10, 2009. W. Chen, R. Dömer: "A Distributed Parallel Simulator for Transaction Level Models with Relaxed Timing", Center for Embedded Computer Systems, Technical Report 11-02, May 2011. R. Dömer: "RIDE: Recoding Integrated Development Environment", Center for Embedded Computer Systems, Technical Report 13-02, April 2013. R. Dömer: "Designer-in-the-Loop Recoding to Create Safe Parallel ESL Models", Invited Tutorial at ASPDAC'14, Singapore, January 20, 2014. R. Dömer: "Foreword", chapter in "Out-of-Order Parallel Discrete Event Simulation for Electronic System-Level Design" by Weiwei Chen, Springer International Publishing Switzerland (ISBN 978-3-319-08752-8), August 2014. Publications Overall, this NSF CAREER project has contributed to a total of 16 technical reports, 3 presentations and tutorials, 1 book chapter, 15 conference papers, 4 journal articles, and 1 book. Moreover, this work has been recognized with a DATE Best Paper Award 2014 and an EDAA Outstanding Dissertation Award 2013. W. Chen, R. Dömer: "ConcurrenC: A New Approach towards Effective Abstraction of C-based SLDLs", Proceedings of the International Embedded Systems Symposium, "Analysis, Architectures and Modeling of Embedded Systems" (ed. A. Rettberg, M. Zanella, M. Amann, M. Keckeisen, F. Rammig), Springer, Langenargen, Germany, September 2009. R. Dömer: "Efficient Modeling of Embedded Systems using Computer-Aided Recoding", Proceedings of the International Embedded Systems Symposium, "Analysis, Architectures and Modeling of Embedded Systems" (ed. A. Rettberg, M. Zanella, M. Amann, M. Keckeisen, F. Rammig), Springer, Langenargen, Germany, September 2009. W. Chen, R. Dömer: "A Fast Heuristic Scheduling Algorithm for Periodic ConcurrenC Models", Proceedings of the Asia and South Pacific Design Automation Conference 2010, Taipei, Taiwan, January 2010. R. Dömer: "Computer-Aided Recoding for Multi-Core Systems", Proceedings of the Asia and South Pacific Design Automation Conference 2010, Taipei, Taiwan, January 2010. W. Chen, X. Han, R. Dömer: "ESL Design and Multi-Core Validation using the System-on-Chip Environment", Proceedings of the International High Level Design Validation and Test Workshop 2010, Anaheim, California, June 2010. R. Dömer, W. Chen, X. Han, A. Gerstlauer: "Multi-Core Parallel Simulation of System-Level Description Languages", Proceedings of the Asia and South Pacific Design Automation Conference 2011, Yokohama, Japan, January 2011. W. Chen, X. Han, R. Dömer: "Multicore Simulation of Transaction-Level Models Using the SoC Environment", IEEE Design & Test of Computers, vol. 28, no. 3, pp. 20-31, May-June 2011. W. Chen, R. Dömer: "An Optimizing Compiler for Out-of-Order Parallel ESL Simulation Exploiting Instance Isolation", Proceedings of the Asia and South Pacific Design Automation Conference 2012, Sydney, Australia, February 2012. R. Dömer, W. Chen, X. Han: "Parallel Discrete Event Simulation of Transaction Level Models", Proceedings of the Asia and South Pacific Design Automation Conference 2012, Sydney, Australia, February 2012. W. Chen, X. Han, R. Dömer: "Out-of-Order Parallel Simulation for ESL Design", Proceedings of Design Automation and Test in Europe, Dresden, Germany, March 2012. R. Dömer: "Recoding Embedded Applications into Flexible System-Level Models", Invited paper, "Quo Vadis, Virtual Platforms?" Workshop at Design Automation and Test in Europe, Dresden, Germany, March 2012. P. Chandraiah, R. Dömer: "Computer-Aided Recoding to Create Structured and Analyzable System Models", ACM Transactions on Embedded Computer Systems, vol. 11S, no. 1, article 23, 27 pages, June 2012. W. Chen, C. Chang, X. Han, R. Dömer: "Eliminating Race Conditions in System-Level Models by using Parallel Simulation Infrastructure", Proceedings of the International High Level Design Validation and Test Workshop 2012, Huntington Beach, California, November 2012. W. Chen, X. Han, C. Chang, R. Dömer: "Advances in Parallel Discrete Event Simulation for Electronic System-Level Design", IEEE Design & Test of Computers, vol. 30, no. 1, pp. 45-54, January-February 2013. W. Chen, R. Dömer: "Optimized Out-of-Order Parallel Discrete Event Simulation Using Predictions", Proceedings of Design, Automation and Test in Europe, Grenoble, France, March 2013. C. Chang, R. Dömer: "Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo Theories", Proceedings of the International Embedded Systems Symposium, "Embedded Systems: Design, Analysis and Verification" (ed. G. Schirner, M. Götz, A. Rettberg, M. Zanella, F. Rammig), Springer, Paderborn, Germany, June 2013. X. Han, W. Chen, R. Dömer: "Designer-in-the-Loop Recoding of ESL Models using Static Parallel Access Conflict Analysis", Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, June 2013. DATE Best Paper Award 2014: W. Chen, X. Han, R. Dömer: "May-Happen-in-Parallel Analysis based on Segment Graphs for Safe ESL Models", Proceedings of Design, Automation and Test in Europe, Dresden, Germany, March 2014. W. Chen, X. Han, C. Chang, G. Liu, R. Dömer: "Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, accepted for publication, July 15, 2014. W. Chen: "Out-of-Order Parallel Discrete Event Simulation for Electronic System-Level Design", Springer International Publishing Switzerland 2015. (ISBN 978-3-319-08752-8, EDAA Outstanding Dissertation Award)

Acknowledgement and Disclaimer:
This material is based upon work supported by the National Science Foundation Grant No. #0747523.
Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.