login(); } if (!empty($_GET['logout'])) { $auth_object->logout(); } // Next, we can check whether or not you're logged // in by checking the $auth->isLoggedIn() method if ($auth_object->isLoggedIn()) { // do stuff, you can check the ucinetid of // the person by looking at $auth->ucinetid if ($auth_object->allowedAccess($auth_object->EECS31L_ARRAY) or $auth_object->allowedAccess($auth_object->EECS31L_STUDENT_ARRAY)) { // don't need to do anything } else { // logged in but not valid... header('Location: ../labs.html'); print "EECS 31L Enrollment Required.

Sorry, you need to be enrolled in EECS 31L in to view this page.

"; exit(); } } else { // you're not logged in, sorry... // try to log user in header('Location: lab3-bRaz53we.html?login=1'); print "EECS 31L Enrollment Required.

Sorry, you need to be enrolled in EECS 31L to view this page.

"; exit(); } // Also, you can look at all the values within // the auth object by using the code: // print "
";
    // print_r ($auth_object);
    // print "
"; // As always, feel free to contact me with questions. // Eric Carter, ecarter@uci.edu ?> Lab 3 :: Labs :: EECS 31L / CSE 31L :: Daniel D. Gajski's Web Site

EECS 31L/CSE 31L: Lab 3 (Winter 2012)

FSMD Lecture Videos for Lab 3

Digital Design Example Video for Lab 3

Lab 3 Handout

Digital Design Refresher for Lab 3

Available on EECS 31/CSE 31 Course Page

Lab 3 Quiz Sample Problems

Problem 1

Question

In the figure below, write Boolean expressions for the Cnt_s, Cnt_d and Cnt_ld so that the Datapath performs up and down counting. The counter counts upwards, downwards or not at all, as follows:

Sample Problem 1 Figure

Solution

Sample Problem 1 Solution Figure

Detailed Explanation

View Video Explanation for Problem 1

Problem 2

Question

Complete the following VHDL code to implement a 4-bit FullAdder unit with data inputs A, B, Cin and outputs F and Cout using two 2-bit FullAdder units as components.

Sample Problem 2 Figure 2 - VHDL Code

Solution

Line # Code
43 Add2_1 : Add_2bit PORT MAP (A(1 downto 0), B(1 downto 0), Cin, F(1 downto 0), C);
44 Add2_2 : Add_2bit PORT MAP (A(3 downto 2), B(3 downto 2), C, F(3 downto 2), Cout);

Detailed Explanation

View Video Explanation for Problem 2

Sample Problem 3

Question

Fix the given code of the 8x16 register file so it models correctly the operation of a register file:

Sample Problem 3 Figure - VHDL Code

Solution

Line # Code
27 ReadProcess: PROCESS(R_Addr, R_en, regfile)

Detailed Explanation

View Video Explanation for Problem 3

Sample Problem 4

In the figure below, write the missing values for input and output control signals in the state machine of the Controller so that the entire design works as an accumulative sum function: sumai The computation starts when control signal Start becomes '1' by moving from Off to Sum state. In state Sum, the Adder in the Datapath adds the numbers from the register file (RegFile) starting from address "0000" to address "0111", according to the values in the Counter. When control signal Eq7 becomes '1', the state machine goes to Output state where it outputs the content of the RegOut register for one clock cycle, after which it returns to the Off state.

Sample Problem 4 Figure

Solution

Sample Problem 4 Figure Solution

Detailed Explanation

View Video Explanation for Problem 4

Sample Problem 5

Sample Problem 4 Figure: table of 4-to-1 SELECTORComplete the following VHDL code to implement a 4-to-1 SELECTOR with data inputs A, B, C, D and a control input SelectCtrl using 2-to-1 SELECTORS as components. Table on the right shows functionality of 4-to-1 SELECTOR.

Sample Problem 5 Figure: 2-to-1 Selector Code

Sample Problem 5 Figure: 4-to-1 Selector Code

Solution

Line # Code
42 Sel1: My_Selector2 PORT MAP (A, B, SelectCtrl(0), sel_out1);
43 Sel2: My_Selector2 PORT MAP (C, D, SelectCtrl(0), sel_out2);
44 Sel3: My_Selector2 PORT MAP (sel_out1, sel_out2, SelectCtrl(1), F);

Detailed Explanation

View Video Explanation for Problem 5