login(); } if (!empty($_GET['logout'])) { $auth_object->logout(); } // Next, we can check whether or not you're logged // in by checking the $auth->isLoggedIn() method if ($auth_object->isLoggedIn()) { // do stuff, you can check the ucinetid of // the person by looking at $auth->ucinetid if ($auth_object->allowedAccess($auth_object->EECS31L_ARRAY) or $auth_object->allowedAccess($auth_object->EECS31L_STUDENT_ARRAY)) { // don't need to do anything } else { // logged in but not valid... header('Location: ../labs.html'); print "EECS 31L Enrollment Required.

Sorry, you need to be enrolled in EECS 31L in to view this page.

"; exit(); } } else { // you're not logged in, sorry... // try to log user in header('Location: lab4-qu2EKe5A.html?login=1'); print "EECS 31L Enrollment Required.

Sorry, you need to be enrolled in EECS 31L to view this page.

"; exit(); } // Also, you can look at all the values within // the auth object by using the code: // print "
";
    // print_r ($auth_object);
    // print "
"; // As always, feel free to contact me with questions. // Eric Carter, ecarter@uci.edu ?> Lab 4 :: Labs :: EECS 31L / CSE 31L :: Daniel D. Gajski's Web Site

EECS 31L/CSE 31L: Lab 4 (Winter 2012)

IP Design Lecture Videos for Lab 4

Digital Design Example Video for Lab 4

Lab 4 Handout

Digital Design Refresher for Lab 4

Available on EECS 31/CSE 31 Course Page

Lab 4 Quiz Sample Problems

Problem 1

Question

The Design below executes the function F = a*b + c + d. The Datapath contains an ALU which can do either addition or multiplication in one clock cycle. Variables a, b, c, and d are stored in the 8 x 16 Register File, where any intermediate result can also be safely stored. Please describe the both non-pipelined and pipelined Datapath operation by specifying the value (expressed by a, b, c, and d) in Reg1, Reg2, and Reg3 for each clock cycle.

Sample Problem 1 Pipeline Figure

Sample Problem 1 Pipeline Table

Solution

Sample Problem 1 Pipeline Table Solution

Detailed Explanation

View Video Explanation for Problem 1

Problem 2

Question

The following VHDL code for the 4-bit adder with carry (Add4wCarry) does not compile and simulate with ModelSim. Rewrite the minimum number of lines to make the entire code compile and simulate correctly.

Sample Problem 2 Figure

Solution

Line # Code
17 A5 := '0' & A; B5 := '0' & B;
18 S5 := A5 + B5 + Ci;

Detailed Explanation

View Video Explanation for Problem 2

Problem 3

Question

The incomplete VHDL code below represents a Sum of Absolute Differences (SAD) component. Complete the VHDL code as described by the commented sections.

Sample Problem 2 VHDL Code

Solution

Line # Code
24 IF (NOT(Go = '1')) THEN
25   WAIT UNTIL Go = '1';
26 END IF;
30 FOR I IN 0 TO 255 LOOP
31   Sum := Sum + Conv_Integer(ABS(A(I) - B(I)));
32 END LOOP;
36 SAD_out <= Sum;

Detailed Explanation

View Video Explanation for Problem 3

Problem 4

Question

In the figure below, write the missing values for input control signals b and Eq2 and output control signals Ld and Sel in the state machine of the Controller so that the entire design works as a timer which starts when control signal b becomes '1' stays in On state for two Clk cycles while output x='1'. When control signal Eq2 becomes '1', the timer returns to Off state where it outputs x='0'.

Sample Problem 2 Figure 2 - VHDL Code

Solution

Sample Problem 2 Figure 2 - VHDL Code Solution

Detailed Explanation

View Video Explanation for Problem 4

Problem 5

Question

The IP design One's Counter (OC) counts the number of 1's in Data. OC's datapath consists of a ShiftReg which shifts data rightward when SR_Right = 1 and loads data when SR_Load = 1, a Counter which counts up when Cn_Count = 1 and resets when Cn_Reset = 1, and a Comparator which outputs 1 when Data value is 0. Complete the controller by specifying the value of 4 control signals SR_Right, SR_Load, Cn_Reset, and Done.

Sample Problem 5 Figure

Sample Problem 5 Control Signals Table

Solution

Sample Problem 5 Control Signals Table Solution

Detailed Explanation

View Video Explanation for Problem 5