EECS 31/CSE 31/ICS 151 Homework 4 Questions

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Problem 1

Question

(Adders) Design a 2-bit adder slice that will combine the functions of two FAs. Using the library presented in Table 3.14, compare the delay of your design with that of the design shown in Figure 5.1.

  1. Write out sum and carry equations for S1, S2 and C1, C2 from X2, Y2, X1, Y1 and C0.
  2. Substitude C1 in S2 and C2 equations with its correspondent expression.
  3. Draw the correspondent logic schematic with AND, OR and XOR gates.
  4. Compute input/output delays.

Problem 2

Question

(Carry-look-ahead generators) Design a 64-bit CLA adder, using:

  1. One level of CLA
  2. Two levels of CLA
  3. Three levels of CLA

Problem 3

Question

(Logic units) Design a logic unit that will perform the following combinations of operations.

  1. NAND, NOR, transfer, and complement
  2. XOR and XNOR

Problem 4

Question

(ALUs) Design an ALU that can perform add, subtract, NAND, and NOR operations.

Problem 5

Question

(Decoders) Design a 4-to-16 decoder, using:

  1. 1-to2 decoders
  2. 2-to-4 decoders

Problem 6

Question

(Comparators) Design the serial and parallel verions of a comprator that can compare the following types of number representation.

  1. Sign-magnitude
  2. Two's complement
  3. Floating point

Problem 7

Question

(Shifters) Design an 8-bit barrel:

  1. Left rotator
  2. Left shifter
  3. Left and right shifter
  4. Left and right shifter/rotator

Problem 8

Question

(ROMs) Using a 16x4 ROM, implement a 2-bit comparator that can generate "greater than," "less than," and "equal to" functions.

Design Synthesis Example

Question

Design a Polite & Stupid Elevator

Assumptions:

  1. There are three floors
  2. Door opens on every floor
  3. One button at any time