Please check the INDEX file(s) for a detailed listing of the technical reports including abstracts.

• Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt and Daniel D. Gajski, "The Effects of Variations om Component Styles and Shapes on High-Level Synthesis," UC Irvine, Technical Report ICS-TR-92-115, December 1992, 24 pages.
• Viraphol Chaiyakul and Daniel D. Gajski, "Assignment Decision Diagram for High-Level Synthesis," UC Irvine, Technical Report ICS-TR-92-103, December 1992, 51 pages.
• Daniel Gajski, Sanjiv Narayan, and Frank Vahid, "A System-Level Specification and Design Methodology," UC Irvine, Technical Report ICS-TR-92-102, October 1992, 22 pages.
• Roger Ang and Nikil Dutt, "On Linking RT-Component Functionality to Abstract HDL Behavior - REVISED," UC Irvine, Technical Report ICS-TR-92-97, July 1993.
• Hsiao-Ping Juan, Nancy Holmes, Smita Bakshi, and Daniel Gajski, "Top-Down Modeling of RISC Processors in VHDL," UC Irvine, Technical Report ICS-TR-92-96, October 1992, 47 pages
• Loganath Ramachandran, Viraphol Chaiyakul, and Daniel D. Gajski, "VHDL Synthesis System (VSS) User's Manual Version 5.0," UC Irvine, Technical Report ICS-TR-92-52, June 1992, 16 pages. ($2.00)
• Loganath Ramachandran and Daniel D. Gajski, "Architectural Tradeoffs in Synthesis of Pipelined Controls," UC Irvine, Technical Report ICS-TR-92-49, May 1992, 22 pages.
• Viraphol Chaiyakul, Daniel D. Gajski, and Loganath Ramachandran, "Minimizing Syntactic Variance with Assignment Decision Diagrams," UC Irvine, Technical Report ICS-TR-92-34, April 1992, 19 pages.
• Pradip K. Jha and Nikil D. Dutt, "A Fast Area-Delay Estimation Technique for RTL Component Generators," UC Irvine, Technical Report ICS-TR-92-33, April 1992, 33 pages.
• Roger Ang and Nikil Dutt, "Transformations Supporting Interactive Rescheduling for High-Level Synthesis," UC Irvine, Technical Report ICS-TR-92-20, February 1992.