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High-level synthesis (HLS) has long relied on {\em point models} for RT-components that assume fixed area and delay values for a given component style. However, aspect ratio variations alone can result in substantially different area-delay characteristics for a component. In this work, we explore the combined effect of style and aspect ratio variations on the area and delay of individual RT-components, as well as on complete RT-level designs produced by HLS. We describe the results of extensive experiments which indicate that point models are inadequate for use in the synthesis process. We believe that our results have some deep implications on the formulation of HLS algorithms that attempt to realistically incorporate physical design information early in the design process.

In the past, the research on representation for synthesis systems had been focusing on two main issues, the completeness and the efficiency. There is, however, another important issue that is not addressed by most of traditional representations, the uniqueness. This report proposes a representation for synthesis called the Assignment Decision Diagram (ADD) that is complete, efficient and partially unique. In addition, the ADD also furnishes many synthesis tasks with information that can simplify the tasks, and can enrich the results of the synthesis. Discussion of ADD's properties and its uses in synthesis is provided in this report.

Given an abstract specification of a system, we present a methodology for specification capture and refinements that will result in synthesizable descriptions. It must be emphasized here that this report is about methodology - the set of descriptions and the manual refinements to derive one description from the other. Some of these refinements can be automated and collected as a set of system-level synthesis tools which are not a part of this report.

Existing High-Level Synthesis (HLS) Systems typically assume a simple representation for the functionality of RT components and for the binding of abstract behavioral (HDL) operators to RT components. Such a representation scheme simplifies synthesis but ignores the problems of representing realistic RT components that may perform several functions and generate several outputs in a single time step. In this paper, we present a novel representation scheme that links realistic RT-component behavior with abstract HDL behavior. It is useful for representing specific components in user-extendable libraries and adapting component libraries to HDL modeling styles. The representation can also be used to support interactive allocation and binding of components during HLS, as well as interactive rebinding of components once a preliminary floorplan is obtained. This allows the designer to iterate between the results of physical design and the higher-level tasks of component allocation and binding. Furthermore, the representation we describe can be used to establish formally the correctness of interactive binding using realistic RT components. We briefly describe the features of the representation and show its applicability on a HLS benchmark -- the AM2901.

In this report, we present a top-down VHDL modeling technique which consists of two main modeling levels: specification level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and effectiveness of this methodology. All models have been simulated on a SPARC~1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibility of the modeling strategy and provide performance measures of RP design features.

This report provides instructions for installing and using the VHDL Synthesis System (Version 5.0). VSS is a high level synthesis system that synthesizes structures from an abstract description, written with VHDL behavioral constructs. The system uses components from a generic component library (GENUS). The output of VSS is in structural VHDL and could be verified using a commercial VHDL simulator. The designer can control the synthesis process by providing different resource constraints to the system. VSS is also capable of producing different architectures which can be selected by the designer.

Many high level synthesis systems produce designs without any consideration for the underlying architecture. In such systems, tradeoffs between area and delay can only be achieved by changing the synthesis constraints (e.g., number of functional units). These systems do not exploit the wider range of tradeoffs that can be achieved by modifying the underlying architecture. In this report we derive a relationship between architectural constraints and scheduling algorithms, and demonstrate how architectural styles impose certain restrictions on the scheduling process. In particular, we consider different control pipelining architectures. We also propose a versatile scheduling algorithm that is capable of synthesizing designs for different control pipelining styles.

Most synthesis generate designs from hardware descriptions by relating each language construct to a particular hardware structure. Thus, designs obtained from these systems are dependent on description styles. In other words, semantically equivalent descriptions with different ordering or grouping of conditional and assignment statements, could generate designs with distinctively different cost and performance. This paper introduces a new representation that minimizes the syntactic variance of different description styles. We also propose an algorithm for conversion of hardware descriptions into this new representation. In addition, using this representation for scheduling results in a drastic reduction on the number of control steps required to synthesize the description. Experimental data on several examples show effectiveness of the proposed approach.

An important benefit of high-level synthesis is rapid design space exploration through examination of different design alternatives. However, such design space exploration is not feasible without fast and accurate area and delay estimates of the synthesized designs. These estimates must factor in physical design effects and technology-specific information in order to achieve accuracy. High-level synthesis tools often use abstract, parameterized component generators for describing the synthesized RT design, and thus need to be supported by fast and accurate estimators for these parameterized RT-components. Ideally, we would like to obtain the actual area and delay attributes of each component by constructing (or generating) the designs. However, such constructive methods require excessive run times, prohibiting on-line integration with the tasks of scheduling and allocation. In this paper, we describe a fast (on-line) method for estimating the area and delay of regular-structured generic RT components that are tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample data points from selected component implementations. We performed an extensive set of experiments to validate our estimation technique on combinational as well as sequential RT component generators. The results show a prediction of the area and delay to within 10high-level synthesis system to permit on-line estimation of a component's area and delay.

Traditionally, high-level synthesis (HLS) has been a fully automatic process over which the user has had little or no control. To make HLS an acceptable methodology for expert designers, we need to allow for more interactivity during synthesis. Since the scheduling step in HLS often determines the scope and quality of the ensuing synthesis tasks, we describe behavior-preserving transformations for manual rescheduling of behavior. We present the Structured Finite State Machine (SFSM) design model for scheduled behavior, show its equivalence to the behavioral Control-Data Flow Graph (CDFG), define primitive behavior-preserving transformations and indicate the utility of these transformations. The manual rescheduling capability we describe allows expert designers to alter an automatically generated schedule to overcome simplifications and assumptions made by automatic scheduling algorithms.