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Lucai Cai, Daniel D. Gajski,
"Introduction of Design-Oriented Profiler of SpecC Language,"
UC Irvine, Technical Report ICS-TR-00-47, June 2001.
To design from higher level of abstraction and to make architecture exploration
decision at early stage, designer should know the characteristics of
specification on the higher level of abstraction. Designers should also have a way to
evaluate the system in early stage, to ensure that the system meets the
constraint requirement. In this report, SpecC profiler, a design-oriented profiler,is
introduced to complete above two tasks, by evaluating the specification model of
"Communication Software Code Generation,"
UC Irvine, Technical Report ICS-TR-00-46, August 2000.
This report describe the implementation of system-level communication
on a programmable processor. First, the issues are introduced using
the example of communication software on a Motorola DSP. Then, the
problem is generalized and defined for the general case of system-level
communication on a programmable processor.
Pei Zhang, Dongwan Shin, Haobo Yu, Qiang Xie, Daniel D. Gajski,
"SpecC RTL Methodology,"
UC Irvine, Technical Report ICS-TR-00-44, December 2000.
This report describes the SpecC RTL methodology, using a specific example
(one's counter). We first begin with the introduction of one's counter. Then the
behavioral view and the structural view of the SpecC implementation model are
given to implement the one's counter in different style. The source codes are also
included in the Appendix.
Hanyu Yin, Haito Du, Tzu-Chia Lee, Daniel D. Gajski,
"Design of a JPEG Encoder using SpecC Methodology,"
UC Irvine, Technical Report ICS-TR-00-23, July 2000.
This report describes the design of a JPEG encoder, using the SpecC
system-level design methodology developed at CADlad, UC Irvine. We
first begin with an executable specification model in SpecC, and then
refine the specification model into an architecture model which
accurately reflects the system architecture. Based on the architecture
model, a communication model where the communication protocols
between the system components are defined is developed. Finally, we
refine the communication model of the DCT block into the implementation
model, which is the lowest level of abstraction in the SpecC methodology.
This project is a result of a course "System Tools" at the Information
and Computer Science departement, UC Irvine.
"SpecC for Beginners: The Example of a Sounding Dice,"
UC Irvine, Technical Report ICS-TR-00-14, May 2000.
In this document the SpecC language is demonstrated in a
low-complexity example with main features of the language explained
and evaluated. The purpose of this document is to give beginners a
first feeling for the language constructs and its
usage in actual modelling. Although the language was not developed for
these small tasks in general, it is well suited to cover all kind of
modelling tasks with the existing semantics. The example consist of
several finite state machines connected and communicating
with each other. The sounding dice example is taken from an existing
design out of the author's course, normally used for student
education in the VHDL classes of the University of Applied Science,
Junyu Peng, Lukai Cai, Anand Selka, Daniel D. Gajski,
"Design of a JBIG Encoder using SpecC Methodology,"
UC Irvine, Technical Report ICS-TR-00-13, June 2000.
This report describes the design of a JBIG encoder, based on theITU-T
Recommendation T.82, using the SpecC system level design methodology
being developed at CAD Lab, UC Irvine. We begin with an executable
specification in SpecC, and explore design alternatives for the system
architecture, and refine the specification into a final communication
model where the communication protocols between the system components
are defined. In this report, we document the different design stages
undergone, and also the results in the process.