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D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao,
"The SpecC Methodology"
UC Irvine, Technical Report ICS-TR-99-56, December 1999.
This report describes the SpecC methodology for system-level embedded system
design. The methodology consists of a set of well-defined tasks and
design models which allow the easy insertion and reuse of intellectual
property. Starting from the abstract executable specification written in SpecC
different design alternatives concerning the system architecture
(components and communication) can be explored and
the specification is gradually refined and mapped to a final HW/SW
implementation such that the constraints are satisfied optimally.
The final hand-off for manufacturing includes software code compiled for
the processors and the RTL descriptions for hardware synthesis.
L. Cai, J. Peng, C. Chang, A. Gerstlauer, H. Li, A. Selka,
C. Siska, L. Sun, S. Zhao and D. Gajski,
"Design of a JPEG Encoding System,"
UC Irvine, Technical Report ICS-TR-99-54, November 1999.
This report describes the design of a JPEG encoder. The project is a
result of a course "System Tools" at Information and Computer
Science Department, UC Irvine. The abstract executable specification
SpecC is first developed based on a public domain C
implementation. Software and hardware estimation is then performed
based on which a datapath architecture is selected and RTL code is
implemented. Finally, to explore the method of implementing a gate level
model, part of the JPEG encoder is refined to the gate
Heiko Lehr and Daniel D. Gajski,
"Modeling Custom Hardware in VHDL,"
UC Irvine, Technical Report ICS-TR-99-29, July 1999.
this report focuses on models for describing Hardware at
different refinement levels within High Level Synthesis flow: SFSMD, FSMD
and FSM Controlling Datapath. Simple data interfaces are often needed in these
models. The hardware description language VHDL is used and tested for
implementing these models and interfaces.
Problems inherent in the models as well as problems caused by VHDL are
discussed. A model related main difficulty is the one-cycle delay of data
processing, when introducing a datapath. VHDL descriptions of abstract models
(SFSMD) can become complicated.
Templates for general problems, examples and VHDL guidelines are provided in
this report to help to minimize design errors significantly.
En-Shou Chang and Daniel D. Gajski,
"SpecC System-level Static Scheduling,"
UC Irvine, Technical Report ICS-TR-99-23, May 1999.
This report describes how to use SpecC System-Level Scheduling (SLS)
tools, as well as definitions of SLS tools, restrictions of current
release, and how to read the refined design generated by SLS tools.
For quick start, two simplified SLS tools provide basic scheduling
functions. However, due to various situations in real designs, we
suggest advance designers use combination of all SLS tools to utilize
all features provided by SLS tools to obtain better results.
Andreas Gerstlauer, Shuqing Zhao, Daniel D. Gajski and Arkady M. Horak,
"Design of a GSM Vocoder using SpecC Methodology,"
UC Irvine, Technical Report ICS-TR-99-11, March 1999.
This report describes the design of a voice encoder/decoder
(vocoder) based on the
European GSM standard employing the system-level design methodology
developed at UC Irvine. The project is a result of a cooperation between
UCI and Motorola to demonstrate the SpecC methodology. Starting from
the abstract executable specification written in SpecC different design
alternatives concerning the system architecture (components and communication)
are explored and
the vocoder specification is gradually refined and mapped to a final HW/SW
implementation such that
the constraints are satisfied optimally.
The final code for downloading onto the processors and the RTL hardware
descriptions for synthesis of the ASICs are generated
for the software and hardware parts, respectively.
Jianwen Zhu and Daniel D. Gajski,
"A Unified Formal Model of ISA and FSMD,"
UC Irvine, Technical Report ICS-TR-99-06, Feburary 1999.
In this report, we develop a formal framework to widen the scope of
retargetable compilation. The goal is achieved by the unification of
architectural models for both the processor architecture and the ASIC
architecture. This framework enables the unified treatment of code
generation and behavioral synthesis, and is being used in our experimental
codesign environment to drive system-on-a-chip synthesis from an
object oriented language.