Disclaimer -- Permission to make digital/hard copy of all or part of any of the following publications and technical reports for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission.

System level synthesis is widely seen as the solution for closing the productivity gap in system design. High-level system models are used in system level design for early design exploration. While real time operating systems (RTOS) are an increasingly important component in system design, specific RTOS implementations cannot be used directly in high level models. On the other hand, existing system level design languages (SLDL) lack support for RTOS modeling.

In this chapter, we propose a RTOS model built on top of existing SLDLs which, by providing the key features typically available in any RTOS, allows the designer to model the dynamic behavior of multi-tasking systems at higher abstraction levels to be incorporated into existing design flows. Experimental result shows that our RTOS model is easy to use and efficient while being able to provide accurate results.

System level design is considered a major approach to tackle the complexity of modern System-on-Chip designs. Embedded software within SoCs is gaining importance as it addresses the increasing need for flexible and feature-rich solutions. Therefore, integrating software design and co-simulation into a system level design flow is highly desirable.

In this article, we present the software perspective within our systemlevel design flow. We address three major aspects: (1) modeling of a processor (from abstract to ISS-based), (2) porting of an RTOS, and (3) the embedded software generation including RTOS targeting.

We describe these aspects based on a case study for the ARM7TDMI processor. We show processor models including a cycle-accurate ISSbased model (using SWARM), which executes the RTOS MicroC/OS-II. We demonstrate our flow with an automotive application of anti-lock breaks using one ECU and CAN-connected sensors. Our experimental results show that automatic SW generation is achievable and that SW designers can utilize the system level benefits. This allows the designer to develop applications more efficiently at the abstract system level.

Much effort in RTL design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button types of synthesis is not accepted by most designers. Interactive design space exploration with assistance of tools and algorithms can be more effective because it provides control of all steps of synthesis.

In this paper, we propose an interactive RTL design environment, which enables designers to control design steps. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. Finally, we present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.

In this paper, we propose automatic generation of bus-based communication architectures from an abstract model reflecting only the communication topology. Tasks include protocol selection for each bus, master/slave assignment for each component, interrupt handling and addressing for synchronization between components, and arbitration to resolve multiple accesses on a bus. We present a set of experimental results demonstrating how the proposed approach works on typical system designs. Experimental results show the benefits of our methodology and demonstrate the effectiveness of automatic model generation for communication design.

System level synthesis is widely seen as the solution for closing the productivity gap in system design. High-level system models are used in system level design for early design exploration. While real time operating systems (RTOS) are an increasingly important component in system design, specific RTOS implementations cannot be used directly in high level models. On the other hand, existing system level design languages (SLDL) lack support for RTOS modeling.

In this chapter, we propose a RTOS model built on top of existing SLDLs which, by providing the key features typically available in any RTOS, allows the designer to model the dynamic behavior of multi-tasking systems at higher abstraction levels to be incorporated into existing design flows. Experimental result shows that our RTOS model is easy to use and efficient while being able to provide accurate results.

The design of embedded systems has to address several interacting design aspects, so-called dimensions, to capture parallelism, distribution over different locations and hard real-time requirements. Thus, a structured design process has been established with the PARADISE design environment. The design process covers all steps from behavioral specification to final chip realization. In this paper, we describe how system specification and refinement is covered in combination with the processes available in PARADISE. An example of an adequate specification and modeling language is considered and adapted for integration into PARADISE. First results show the feasibility of integrating the respective concepts.

In this paper, we demonstrate the application of the specify-explore-refine (SER) paradigm for an IP-centric codesign of embedded systems. We describe the necessary design tasks required to map an abstract executable specification of the system to the architectural implementation model. We also describe the final and intermediate models generated as a result of these design tasks. The executable specification and its refinements should support easy insertion and reuse of IPs.
     Although several languages are currently used for system design, none of them completely meets the unique requirements of system modelling with support for IP reuse. This paper discusses the requirements and objectives for system languages and describes a C-based language called SpecC, which precisely covers these requirements in an orthogonal manner.
     Finally, we describe the design environment which is based on our codesign methodology.