ARCHITECTURE FOR AREA-EFFICIENT 2-D TRANSFORM IN H.264/AVC (FriAmPO1)

Author(s) : Yu-Ting Kuo (DEE, NCTU, Taiwan) Tay-Jyi Lin (DEE, NCTU, Taiwan) Chih-Wei Liu (DEE, NCTU, Taiwan) Chein-Wei Jen (STC, ITRI, Taiwan)

Abstract : As the VLSI technology advances, the gate delay decreases, but the wire delay significantly increases and has become predominant in modern designs. Conventional ASIC design methodology starting from the minimization of algorithmic operations (e.g. multiply) may not always lead to optimal architectures as before. This paper explores algorithms and architectures for the 2-D transform in H.264/AVC, of which the operations are very simple (i.e. only shift and add), and proposes a data-serial architecture for direct computations. In our experiments with the UMC 0.18£gm CMOS technology, the most straightforward matrix multiplication without any separable 2-D operation or fast algorithm has the best area efficiency. For D1-size (720¡Ñ480) and 30fps frame rate, the proposed architecture can save 34% and 16% silicon area of the previous works.

Menu