SIGDA Super Compendium, FPGA 1996, Author Index

<BODY> <H3><A HREF="../../../../../main_ss.htm">CDROM Home Page</A></BR> <A HREF="../../../comp96ss.htm">1996 Compendium Index</A></BR> FPGA 96 : [<A HREF="fpgatoc.htm">Table of Contents</A> ] [<A HREF="fpgaabs.htm">Abstracts</A> ] [<A HREF="fpgasess.htm">Session Index</A> ]</H3> <HR> <H2>AUTHOR INDEX FPGA 96</H2> <B> <A HREF="#A">[A]</A> <A HREF="#B">[B]</A> <A HREF="#C">[C]</A> <A HREF="#D">[D]</A> <A HREF="#H">[H]</A> <A HREF="#K">[K]</A> <A HREF="#L">[L]</A> <A HREF="#M">[M]</A> <A HREF="#P">[P]</A> <A HREF="#R">[R]</A> <A HREF="#S">[S]</A> <A HREF="#T">[T]</A> <A HREF="#V">[V]</A> <A HREF="#W">[W]</A> <A HREF="#Y">[Y]</A> <A HREF="#Z">[Z]</A><P> </B> <hr> <DL><H1><A NAME="A">A</A></H1> <DT><B>Abramovici, M.</B> <DD><A HREF="fpgaabs.htm#5b_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_2.psz"> <I>Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks</I></A> <DT><B>Albertson, L.</B> <DD><A HREF="fpgaabs.htm#1_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_2.psz"> <I>Plasma: An FPGA for Million Gate Systems</I></A> <DT><B>Amerson, R.</B> <DD><A HREF="fpgaabs.htm#1_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_2.psz"> <I>Plasma: An FPGA for Million Gate Systems</I></A> <DT><B>Ashen, D.</B> <DD><A HREF="fpgaabs.htm#5b_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_1.psz"> <I>Diagnosing Programmable Interconnect Systems for FPGAs</I></A> <DT><B>Azegami, K.</B> <DD><A HREF="fpgaabs.htm#1_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_3.psz"> <I>Flexible FPGA Architecture Realized of General Purpose Sea of Gates</I></A> </DL> <HR> <DL><H1><A NAME="B">B</A></H1> <DT><B>Boemo, E.I.</B> <DD><A HREF="fpgaabs.htm#3_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/3_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/3_1.psz"> <I>The Wave Pipeline Effect on LUT-Based FPGA Architectures</I></A> <DT><B>Bratt, A.</B> <DD><A HREF="fpgaabs.htm#5a_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5a_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5a_1.psz"> <I>Design and Implementation of a Field-Programmable Analogue Array</I></A> <DT><B>Brown, S.</B> <DD><A HREF="fpgaabs.htm#1_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_1.psz"> <I>Hybrid FPGA Architecture</I></A> </DL> <HR> <DL><H1><A NAME="C">C</A></H1> <DT><B>Carter, R.</B> <DD><A HREF="fpgaabs.htm#1_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_2.psz"> <I>Plasma: An FPGA for Million Gate Systems</I></A> <DT><B>Chan, V.C.</B> <DD><A HREF="fpgaabs.htm#3_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/3_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/3_2.psz"> <I>Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays</I></A> <DT><B>Chang, Y.W.</B> <DD><A HREF="fpgaabs.htm#4_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/4_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/4_3.psz"> <I>Universal Switch-Module Design for Symmetric-Array Based FPGAs</I></A> <DT><B>Chen, P.</B> <DD><A HREF="fpgaabs.htm#5b_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_2.psz"> <I>Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks</I></A> <DT><B>Chen, X.</B> <DD><A HREF="fpgaabs.htm#5b_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_1.psz"> <I>Diagnosing Programmable Interconnect Systems for FPGAs</I></A> <DT><B>Cong, J.</B> <DD><A HREF="fpgaabs.htm#8_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/8_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/8_1.psz"> <I>RASP: A General Logic Synthesis System for SRAM-based FPGAs</I></A> <DT><B>Cronquist, D.</B> <DD><A HREF="fpgaabs.htm#8_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/8_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/8_2.psz"> <I>Emerald - An Architecture-Driven Tool Compiler for FPGAs</I></A> <DT><B>Culbertson, W.</B> <DD><A HREF="fpgaabs.htm#1_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_2.psz"> <I>Plasma: An FPGA for Million Gate Systems</I></A> </DL> <HR> <DL><H1><A NAME="D">D</A></H1> <DT><B>Dai, W.W-M.</B> <DD><A HREF="fpgaabs.htm#4_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/4_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/4_1.psz"> <I>A Method for Generating Random Circuits and Its Application to Routability Measurement</I></A> <DT><B>Darnauer, J.</B> <DD><A HREF="fpgaabs.htm#4_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/4_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/4_1.psz"> <I>A Method for Generating Random Circuits and Its Application to Routability Measurement</I></A> <DT><B>DeHon, A.</B> <DD><A HREF="fpgaabs.htm#4_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/4_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/4_2.psz"> <I>Entropy, Counting, and Programmable Interconnect</I></A> <DD><A HREF="fpgaabs.htm#7_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/7_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/7_1.psz"> <I>DPGA Utilization and Application</I></A> <DT><B>Dick, C. </B> <DD><A HREF="fpgaabs.htm#7_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/7_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/7_3.psz"> <I>Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays</I></A> <DT><B>Ding, Y.</B> <DD><A HREF="fpgaabs.htm#8_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/8_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/8_1.psz"> <I>RASP: A General Logic Synthesis System for SRAM-based FPGAs</I></A> </DL> <HR> <DL><H1><A NAME="H">H</A></H1> <DT><B>Huang, W.K.</B> <DD><A HREF="fpgaabs.htm#5b_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_1.psz"> <I>Diagnosing Programmable Interconnect Systems for FPGAs</I></A> <DT><B>Hutchings, B.L.</B> <DD><A HREF="fpgaabs.htm#7_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/7_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/7_2.psz"> <I>Sequencing Run-Time Reconfigured Hardware with Software</I></A> </DL> <HR> <DL><H1><A NAME="K">K</A></H1> <DT><B>Kashiwakura, S.</B> <DD><A HREF="fpgaabs.htm#1_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_3.psz"> <I>Flexible FPGA Architecture Realized of General Purpose Sea of Gates</I></A> <DT><B>Kaviani, A.</B> <DD><A HREF="fpgaabs.htm#1_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_1.psz"> <I>Hybrid FPGA Architecture</I></A> <DT><B>Klein, H.W.</B> <DD><A HREF="fpgaabs.htm#5a_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5a_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5a_2.psz"> <I>The EPAC Architecture: An Expert Cell Approach to Field-Programmable Analog Devices</I></A> <DT><B>Koch, A.</B> <DD><A HREF="fpgaabs.htm#8_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/8_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/8_3.psz"> <I>Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs</I></A> <DT><B>Konala, S.</B> <DD><A HREF="fpgaabs.htm#5b_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_2.psz"> <I>Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks</I></A> <DT><B>Kuekes, P.</B> <DD><A HREF="fpgaabs.htm#1_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_2.psz"> <I>Plasma: An FPGA for Million Gate Systems</I></A> </DL> <HR> <DL><H1><A NAME="L">L</A></H1> <DT><B>Lewis, D.M.</B> <DD><A HREF="fpgaabs.htm#3_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/3_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/3_2.psz"> <I>Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays</I></A> <DT><B>Liu, C.L.</B> <DD><A HREF="fpgaabs.htm#3_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/3_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/3_3.psz"> <I>Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance</I></A> <DT><B>Lombardi, F.</B> <DD><A HREF="fpgaabs.htm#5b_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_1.psz"> <I>Diagnosing Programmable Interconnect Systems for FPGAs</I></A> <DT><B>Lopez-Buedo, S.</B> <DD><A HREF="fpgaabs.htm#3_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/3_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/3_1.psz"> <I>The Wave Pipeline Effect on LUT-Based FPGA Architectures</I></A> </DL> <HR> <DL><H1><A NAME="M">M</A></H1> <DT><B>Macbeth, I.</B> <DD><A HREF="fpgaabs.htm#5a_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5a_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5a_1.psz"> <I>Design and Implementation of a Field-Programmable Analogue Array</I></A> <DT><B>McMurchie, L.</B> <DD><A HREF="fpgaabs.htm#8_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/8_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/8_2.psz"> <I>Emerald - An Architecture-Driven Tool Compiler for FPGAs</I></A> <DT><B>Meneses, J.M.</B> <DD><A HREF="fpgaabs.htm#3_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/3_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/3_1.psz"> <I>The Wave Pipeline Effect on LUT-Based FPGA Architectures</I></A> </DL> <HR> <DL><H1><A NAME="P">P</A></H1> <DT><B>Pan, P.</B> <DD><A HREF="fpgaabs.htm#3_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/3_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/3_3.psz"> <I>Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance</I></A> <DT><B>Peck, J.</B> <DD><A HREF="fpgaabs.htm#8_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/8_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/8_1.psz"> <I>RASP: A General Logic Synthesis System for SRAM-based FPGAs</I></A> </DL> <HR> <DL><H1><A NAME="R">R</A></H1> <DT><B>Rosenstiel, W.</B> <DD><A HREF="fpgaabs.htm#2_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/2_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/2_3.psz"> <I>Combined Spectral Techniques for Boolean Matching</I></A> </DL> <HR> <DL><H1><A NAME="S">S</A></H1> <DT><B>Schubert, E.</B> <DD><A HREF="fpgaabs.htm#2_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/2_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/2_3.psz"> <I>Combined Spectral Techniques for Boolean Matching</I></A> <DT><B>Snider, G.</B> <DD><A HREF="fpgaabs.htm#1_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_2.psz"> <I>Plasma: An FPGA for Million Gate Systems</I></A> <DT><B>Stroud, C.</B> <DD><A HREF="fpgaabs.htm#5b_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/5b_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/5b_2.psz"> <I>Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks</I></A> </DL> <HR> <DL><H1><A NAME="T">T</A></H1> <DT><B>Thakur, S.</B> <DD><A HREF="fpgaabs.htm#2_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/2_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/2_2.psz"> <I>Universal Logic Modules for Series-Parallel Functions</I></A> </DL> <HR> <DL><H1><A NAME="V">V</A></H1> <DT><B>Vranesic, Z.G.</B> <DD><A HREF="fpgaabs.htm#2_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/2_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/2_1.psz"> <I>Using BDDs to Design ULMs for FPGAs</I></A> </DL> <HR> <DL><H1><A NAME="W">W</A></H1> <DT><B>Wirthlin, M.J.</B> <DD><A HREF="fpgaabs.htm#7_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/7_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/7_2.psz"> <I>Sequencing Run-Time Reconfigured Hardware with Software</I></A> <DT><B>Wong, C.K.</B> <DD><A HREF="fpgaabs.htm#4_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/4_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/4_3.psz"> <I>Universal Switch-Module Design for Symmetric-Array Based FPGAs</I></A> <DT><B>Wong, D.F.</B> <DD><A HREF="fpgaabs.htm#2_2"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/2_2.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/2_2.psz"> <I>Universal Logic Modules for Series-Parallel Functions</I></A> <DD><A HREF="fpgaabs.htm#4_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/4_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/4_3.psz"> <I>Universal Switch-Module Design for Symmetric-Array Based FPGAs</I></A> </DL> <HR> <DL><H1><A NAME="Y">Y</A></H1> <DT><B>Yamashita, K.</B> <DD><A HREF="fpgaabs.htm#1_3"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/1_3.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/1_3.psz"> <I>Flexible FPGA Architecture Realized of General Purpose Sea of Gates</I></A> </DL> <HR> <DL><H1><A NAME="Z">Z</A></H1> <DT><B>Zilic, Z.</B> <DD><A HREF="fpgaabs.htm#2_1"><IMG SRC="../../../absicon.gif"></A> <A HREF="../../pdffiles/2_1.pdf"><IMG SRC="../../../pdficon.gif"></A> <A HREF="../../psfiles/2_1.psz"> <I>Using BDDs to Design ULMs for FPGAs</I></A>