SIGDA Super Compendium, DAC 1995, Table of Contents

<body> <h3><a href="../../../../../main_ss.htm">CDROM Home Page </a></br> <a href="../../../comp95ss.htm">1995 Compendium Index</a></br> DAC '95: [ <a href="dacabs.htm">Abstracts</a> ] [ <a href="dacsess.htm">Session Index</a> ] [ <a href="dacai.htm">Author Index</a> ]</h3> <hr> <h2>TABLE OF CONTENTS DAC '95</h2> <b> Sessions</br> <a href="#sess1">[1]</a> <a href="#sess2">[2]</a> <a href="#sess3">[3]</a> <a href="#sess4">[4]</a> <a href="#sess5">[5]</a> <a href="#sess6">[6]</a> <a href="#sess7">[7]</a> <a href="#sess8">[8]</a> <a href="#sess9">[9]</a> <a href="#sess10">[10]</a> <a href="#sess11">[11]</a> <a href="#sess12">[12]</a> <a href="#sess13">[13]</a> <a href="#sess14">[14]</a> <a href="#sess15">[15]</a> <a href="#sess16">[16]</a> <a href="#sess17">[17]</a> <a href="#sess18">[18]</a> <a href="#sess19">[19]</a> <a href="#sess20">[20]</a> <a href="#sess21">[21]</a> <a href="#sess22">[22]</a> <a href="#sess23">[23]</a> <a href="#sess24">[24]</a> <a href="#sess25">[25]</a> <a href="#sess26">[26]</a> <a href="#sess27">[27]</a> <a href="#sess28">[28]</a> <a href="#sess29">[29]</a> <a href="#sess30">[30]</a> <a href="#sess31">[31]</a> <a href="#sess32">[32]</a> <a href="#sess33">[33]</a> <a href="#sess34">[34]</a> <a href="#sess35">[35]</a> <a href="#sess36">[36]</a> <a href="#sess37">[37]</a> <a href="#sess38">[38]</a> <a href="#sess39">[39]</a> <a href="#sess40">[40]</a> <a href="#sess41">[41]</a><p> za href="../../psfiles/front.pdf">Executive Committee</a><br> <a href="../../psfiles/front.pdf">General Chair's Welcome</a><br> <a href="../../psfiles/front.pdf">Technical Program Committee</a><br> <a href="../../psfiles/front.pdf">ACM Awards/Fellows and IEEE Fellows</a><br> <a href="../../psfiles/front.pdf">1995 Best Paper Award</a><br> <a href="../../psfiles/front.pdf">Design Automation Conference Scholarship Awards</a><br> <a href="../../psfiles/front.pdf">Reviewers</a><br> <a href="../../psfiles/front.pdf">1995 Keynote Address--A. Richard Newton</a> </b> <p> *Best Paper Award Candidate<p> <hr> <h3>Session 1 <a href="dacabs.htm#sess1" name="sess1">Panel: Executive Perspective on the Future of the EDA Industry and Design Technology</a></h3> <i>Chair: Ron Collett</i><br> <i>Panelists: Joe Costello, Aart DeGeus, Alain Hanover, Gerry Hsu, Wally Rhines</i><p> <hr> <h3>Session 2 <a href="dacabs.htm#sess2" name="sess2">Design of UltraSPARC</a></h3> <i>Chair: Nigel Ross</i><p> <a href="dacabs.htm#02_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/02_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 2.1 A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC(TM)-I </a><br> <i>Marc Tremblay, Guillermo Maturana, Atsushi Inoue, Les Kohn</i><p> <a href="dacabs.htm#02_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/02_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 2.2 System Design Methodology of UltraSPARC(TM)-I </a><br> <i>Lawrence Yang, David Gao, Jamshid Mostoufi, Raju Joshi, Paul Loewenstein</i><p> <a href="dacabs.htm#02_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/02_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 2.3 UltraSPARC(TM)™-I Emulation </a><br> <i>James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, , Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong</i><p> <a href="dacabs.htm#02_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/02_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 2.4 CAD Methodology for the Design of UltraSPARC(TM)-I Microprocessor at Sun Microsystems Inc. </a><br> <i>A.Cao, A.Adalal, J.Bauman, P.Delisle, P.Dedood, P.Donehue, M.Dell'Oca Khouja, T.Doan, M.Doreswamy, P.Ferolito, O.Geva, D.Greenhill, S.Gopaladhine, J.Irwin, L.Lev, J.MacDonald, M.Ma, S.Mitra, P.Patel, A.Prabhu, R.Puranik, S.Rozanski, N.Ross, P.Saggurti, S.Simovich, R.Sunder, B.Sur, W.Vercruysse, M.Wong, P.Yip, R.Yu, J.Zhou, G.Zyner</i><p> <hr> <h3>Session 3 <a href="dacabs.htm#sess3" name="sess3">Power Considerations in Synthesis</a></h3> <i>Chair: Jan Rabaey</i><p> <a href="dacabs.htm#03_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/03_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 3.1 Computing the Maximum Power Cycles of a Sequential Circuit </a><br> <i>Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino</i><p> <a href="dacabs.htm#03_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/03_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 3.2 Register Allocation and Binding for Low Power </a><br> <i>Jui-Ming Chang, Massoud Pedram</i><p> <a href="dacabs.htm#03_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/03_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 3.3 Memory Segmentation to Exploit Sleep Mode Operation </a><br> <i>Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh</i><p> <a href="dacabs.htm#03_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/03_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 3.4 Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level </a><br> <i>Raul San Martin, John P. Knight</i><p> <hr> <h3>Session 4 <a href="dacabs.htm#sess4" name="sess4">Technology and Layout Dependent Synthesis</a></h3> <i>Chair: Gabriele Saucier</i><p> <a href="dacabs.htm#04_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/04_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 4.1 Boolean Matching for Incompletely Specified Functions* </a><br> <i>Kuo-Hua Wang, TingTing Hwang</i><p> <a href="dacabs.htm#04_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/04_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 4.2 Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm* </a><br> <i>Bernd Wurth, Klaus Eckl, Kurt Antreich</i><p> <a href="dacabs.htm#04_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/04_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 4.3 A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis </a><br> <i>Ted Stanion, Carl Sechen</i><p> <a href="dacabs.htm#04_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/04_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 4.4 Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping </a><br> <i>Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao</i><p> <a href="dacabs.htm#04_5"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/04_5.pdf"><img src="../../../../../icons/pdficon.gif"></a> 4.5 Minimizing the Routing Cost during Logic Extraction </a><br> <i>Hirendu Vaishnav, Massoud Pedram</i><p> <hr> <h3>Session 5 <a href="dacabs.htm#sess5" name="sess5">Issues in EDA Frameworks</a></h3> <i>Chair: Ken Slater</i><p> <a href="dacabs.htm#05_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/05_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 5.1 Requirements-Based Design Evaluation </a><br> <i>Stephen T. Frezza, Steven P. Levitan, Panos K. Chrysanthis</i><p> <a href="dacabs.htm#05_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/05_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 5.2 Incorporating Design Schedule Management into a Flow Management System </a><br> <i>Eric W. Johnson, Jay B. Brockman</i><p> <a href="dacabs.htm#05_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/05_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 5.3 Generating ECAD Framework Code from Abstract Models </a><br> <i>Joachim Altmeyer, Bernd Schürmann, Martin Schütze</i><p> <a href="dacabs.htm#05_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/05_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 5.4 Tool Integration and Construction Using Generated Graph-Based Design Representations </a><br> <i>Ansgar Bredenfeld, Raul Camposano</i><p> <hr> <h3>Session 6 <a href="dacabs.htm#sess6" name="sess6">Panel: Managing Design Change - Lessons Learned</a></h3> <i>Chair: Donald Reinertsen</i><br> <i>Panelists: Franz Fink, John Lods, Thomas P. Pennino, Dave Rollenhagen</i><p></i><p> <hr> <h3>Session 7 <a href="dacabs.htm#sess7" name="sess7">Scheduling and Retiming in Architectural Synthesis</a></h3> <i>Chair: David Ku</i><p> <a href="dacabs.htm#07_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/07_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 7.1Scheduling Using Behavioral Templates* </a><br> <i>Tai Ly, David Knapp, Ron Miller, Don MacMillen</i><p> <a href="dacabs.htm#07_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/07_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 7.2 Rephasing: A Transformation Technique for the Manipulation of Timing Constraints* </a><br> <i>Miodrag Potkonjak, Mani Srivastava</i><p> <a href="dacabs.htm#07_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/07_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 7.3 Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming </a><br> <i>Y.G. DeCastelo-Vide-e-Souza, M. Potkonjak Alice C. Parker</i><p> <hr> <h3>Session 8 <a href="dacabs.htm#sess8" name="sess8">Delay Test and Diagnosis</a></h3> <i>Chair: Peter C. Maxwell</i><p> <a href="dacabs.htm#08_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/08_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 8.1 Fast Identification of Robust Dependent Path Delay Faults </a><br> <i>U. Sparmann, D. Luxenburger, K.-T. Cheng, S.M. Reddy</i><p> <a href="dacabs.htm#08_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/08_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 8.2 On Synthesis-for-Testability of Combinational Logic Circuits </a><br> <i>Irith Pomeranz, Sudhakar M. Reddy</i><p> <a href="dacabs.htm#08_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/08_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 8.3 Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists </a><br> <i>Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel</i><p> <hr> <h3>Session 9 <a href="dacabs.htm#sess9" name="sess9">Discrete-Event Simulation</a></h3> <i>Chair: Peter M. Maurer</i><p> <a href="dacabs.htm#09_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/09_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 9.1 Tutorial: Parallel Logic Simulation of VLSI Systems </a><br> <i>Roger D. Chamberlain</i><p> <a href="dacabs.htm#09_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/09_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 9.2 Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors </a><br> <i>Peter A. Walker, Sumit Ghosh</i><p> <a href="dacabs.htm#09_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/09_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 9.3 A General Method for Compiling Event-Driven Simulations </a><br> <i>Robert S. French, Monica S. Lam, Jeremy R. Levitt, Kunle Olukotun</i><p> <hr> <h3>Session 10 <a href="dacabs.htm#sess10" name="sess10">Panel: Power Minimization in IC Design</a></h3> <i>Chair: Massoud Pedram</i><br> <i>Panelists: Walter Davis, Adel Khouja, Uming Ko, Raymond Leung, Simon Napper, Stefaan Note, Jan Rabaey</i><p> <hr> <h3>Session 11 <a href="dacabs.htm#sess11" name="sess11">Storage Synthesis and Optimization</a></h3> <i>Chair: F. Kurdahi</i><p> <a href="dacabs.htm#11_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/11_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 11.1 A Transformation-Based Approach for Storage Optimization </a><br> <i>Wei-Kai Cheng, Youn-Long Lin</i><p> <a href="dacabs.htm#11_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/11_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 11.2 Register Minimization beyond Sharing among Variables </a><br> <i>Tsung-Yi Wu, Youn-Long Lin</i><p> <a href="dacabs.htm#11_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/11_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 11.3 Constrained Register Allocation in Bus Architectures </a><br> <i>Elof Frank, Salil Raje, Majid Sarrafzadeh</i><p> <hr> <h3>Session 12 <a href="dacabs.htm#sess12" name="sess12">Retiming and Sequential ATPG</a></h3> <i>Chair: Sandip Kundu</i><p> <a href="dacabs.htm#12_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/12_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 12.1 On Test Set Preservation of Retimed Circuits </a><br> <i>Aiman El-Maleh, Thomas Marchok, Janusz Rajski, Wojciech Maly</i><p> <a href="dacabs.htm#12_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/12_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 12.2 Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation </a><br> <i>Elizabeth M. Rudnick, Janak H. Patel</i><p> <a href="dacabs.htm#12_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/12_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 12.3 Partial Scan with Pre-selected Scan Signals </a><br> <i>Peichen Pan, C. L. Liu</i><p> <hr> <h3>Session 13 <a href="dacabs.htm#sess13" name="sess13">Partitioning and Placement</a></h3> <i>Chair: Antun Domic</i><p> <a href="dacabs.htm#13_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/13_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 13.1 Spectral Partitioning: The More Eigenvectors, the Better* </a><br> <i>Charles J. Alpert, So-Zen Yao</i><p> <a href="dacabs.htm#13_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/13_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 13.2 Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs </a><br> <i>Prashant Sawkar, Donald Thomas</i><p> <a href="dacabs.htm#13_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/13_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 13.3 Performance-Driven Partitioning Using a Replication Graph Approach </a><br> <i>Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, Te C. Hu</i><p> <a href="dacabs.htm#13_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/13_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 13.4 Timing Driven Placement for Large Standard Cell Circuits </a><br> <i>William Swartz, Carl Sechen</i><p> <a href="dacabs.htm#13_5"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/13_5.pdf"><img src="../../../../../icons/pdficon.gif"></a> 13.5 Quantified Suboptimality of VLSI Layout Heuristics </a><br> <i>Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng</i><p> <hr> <h3>Session 14 <a href="dacabs.htm#sess14" name="sess14">Design Case Studies</a></h3> <i>Chair: Scott Nance</i><p> <a href="dacabs.htm#14_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/14_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 14.1 Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation </a><br> <i>Thomas W. Albrecht</i><p> <a href="dacabs.htm#14_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/14_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 14.2 Digital Receiver Design Using VHDL Generation from Data Flow Graphs* </a><br> <i>Peter Zepter, Thorsten Grötker, Heinrich Meyr</i><p> <a href="dacabs.htm#14_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/14_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 14.3 Logic Verification Methodology for PowerPC™ Microprocessors </a><br> <i>Charles H. Malley, Max Dieudonné</i><p> <hr> <h3>Session 15 <a href="dacabs.htm#sess15" name="sess15">Panel: University-Industry Ties: How Can They Be Improved?</a></h3> <i>Chair: Randal E. Bryant</i><br> <i>Panelists: Richard Bushroe, John Darringer, Daniel D. Gajski, Robert Hum, Tokinori Kozawa, Alberto L. Sangiovanni-Vincentelli, John Toole </i><p> <hr> <h3>Session 16 <a href="dacabs.htm#sess16" name="sess16">Low Power Design</a></h3> <i>Chair: Suresh Rajgopal</i><p> <a href="dacabs.htm#16_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/16_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 16.1 Tutorial: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits </a><br> <i>Srinivas Devadas, Sharad Malik</i><p> <a href="dacabs.htm#16_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/16_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 16.2 Logic Extraction and Factorization for Low Power </a><br> <i>Sasan Iman, Massoud Pedram</i><p> <a href="dacabs.htm#16_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/16_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 16.3 Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool </a><br> <i>Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli</i><p> <hr> <h3>Session 17 <a href="dacabs.htm#sess17" name="sess17">Extraction and Module Generation</a></h3> <i>Chair: Youn-Long Lin</i><p> <a href="dacabs.htm#17_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/17_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 17.1 The Aurora RAM Compiler </a><br> <i>Ajay Chandna, C. David Kibler, Richard B. Brown, Mark Roberts, Karem A. Sakallah</i><p> <a href="dacabs.htm#17_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/17_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 17.2 Automatic Layout Synthesis of Leaf Cells </a><br> <i>Sanjay Rekhi, J. Donald Trotter, Daniel H. Linder</i><p> <a href="dacabs.htm#17_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/17_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 17.3 Delayed Frontal Solution for Finite-Element Based Resistance Extraction </a><br> <i>N.P. van der Meijs, A.J. van Genderen</i><p> <hr> <h3>Session 18 <a href="dacabs.htm#sess18" name="sess18">Advanced Methods in Practice</a></h3> <i>Chair: Don Stark</i><p> <a href="dacabs.htm#18_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/18_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 18.1 Test Program Generation for Functional Verification of PowerPC Processors in IBM* </a><br> <i>Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek</i><p> <a href="dacabs.htm#18_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/18_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 18.2Behavioral Synthesis Methodology for HDL-Based Specification and Validation* </a><br> <i>D. Knapp, T. Ly, D. MacMillen, R. Miller</i><p> <a href="dacabs.htm#18_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/18_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 18.3 Design-Flow and Synthesis for ASICs: A Case Study </a><br> <i>Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza</i><p> <a href="dacabs.htm#18_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/18_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 18.4 Model Checking in Industrial Hardware Design </a><br> <i>Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl</i><p> <hr> <h3>Session 19 <a href="dacabs.htm#sess19" name="sess19">Sequential Logic Synthesis</a></h3> <i>Chair: Narendra Shenoy</i><p> <a href="dacabs.htm#19_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/19_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 19.1 DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling*</a><br> <i>Kumar N. Lalgudi, Marios C. Papaefthymiou</i><p> <a href="dacabs.htm#19_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/19_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 19.2 A Fresh Look at Retiming Via Clock Skew Optimization </a><br> <i>Rahul B. Deokar, Sachin S. Sapatnekar</i><p> <a href="dacabs.htm#19_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/19_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 19.3 The Validity of Retiming Sequential Circuits </a><br> <i>Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton</i><p> <a href="dacabs.htm#19_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/19_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 19.4 Retiming Synchronous Circuitry with Imprecise Delays </a><br> <i>I. Karkowski, R.H.J.M. Otten</i><p> <a href="dacabs.htm#19_5"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/19_5.pdf"><img src="../../../../../icons/pdficon.gif"></a> 19.5 A Fast State Assignment Procedure for Large FSMs </a><br> <i>Shihming Liu, Massoud Pedram, Alvin M. Despain</i><p> <hr> <h3>Session 20 <a href="dacabs.htm#sess20" name="sess20">Fault Modeling and Simulation</a></h3> <i>Chair: M. Ray Mercer</i><p> <a href="dacabs.htm#20_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/20_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 20.1 Software Accelerated Functional Fault Simulation for Data-Path Architectures </a><br> <i>M. Kassab, N. Mukherjee, J. Rajski, J. Tyszer</i><p> <a href="dacabs.htm#20_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/20_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 20.2 Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy </a><br> <i>R. Krieger, B. Becker, M. Keim</i><p> <a href="dacabs.htm#20_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/20_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 20.3 Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks </a><br> <i>Haluk Konuk, F. Joel Ferguson, Tracy Larrabee</i><p> <a href="dacabs.htm#20_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/20_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 20.4 Analysis of Switch-Level Faults by Symbolic Simulation </a><br> <i>Lluís Ribas-Xirgo, Jordi Carrabina-Bordoll</i><p> <hr> <h3>Session 21 <a href="dacabs.htm#sess21" name="sess21">CAD for Interconnect</a></h3> <i>Chair: Andrzej J. Strojwas</i><p> <a href="dacabs.htm#21_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/21_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 21.1 Transmission Line Synthesis </a><br> <i>Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi</i><p> <a href="dacabs.htm#21_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/21_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 21.2 The Elmore Delay as a Bound for RC Trees with Generalized Input Signals </a><br> <i>Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi</i><p> <a href="dacabs.htm#21_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/21_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 21.3 Delay Analysis of the Distributed RC Line </a><br> <i>Vasant B. Rao</i><p> <a href="dacabs.htm#21_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/21_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 21.4 Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures </a><br> <i>L. Miguel Silveira, Matton Kamon, Jacob White</i><p> <a href="dacabs.htm#21_5"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/21_5.pdf"><img src="../../../../../icons/pdficon.gif"></a> 21.5 Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs </a><br> <i>Sharad Mehrotra, Paul Franzon, Michael Steer</i><p> <hr> <h3>Session 22 <a href="dacabs.htm#sess22" name="sess22">Tutorial: ASIC Prototyping</a></h3> <i>Chair: Gabriele Saucier</i><br> <i>Presenters: Jack Donovan, Haz Nabulsi, Vincent Olive, Gabriele Saucier, Ralph Zak</i><p> <hr> <h3>Session 23 <a href="dacabs.htm#sess23" name="sess23">Datapath Synthesis and Modeling</a></h3> <i>Chair: Robert A. Walker</i><p> <a href="dacabs.htm#23_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/23_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 23.1Symbolic Modeling and Evaluation of Data Paths*</a><br> <i>Chuck Monahan, Forrest Brewer</i><p> <a href="dacabs.htm#23_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/23_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 23.2 Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead </a><br> <i>Ishwar Parulkar, Sandeep Gupta, Melvin A. Breuer</i><p> <a href="dacabs.htm#23_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/23_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 23.3 Deriving Efficient Area and Delay Estimates by Modeling Layout Tools</a><br> <i>Donald S. Gelosh, Dorothy E. Setliff</i><p> <hr> <h3>Session 24 <a href="dacabs.htm#sess24" name="sess24">Learning and Counterexamples in Formal Verification</a></h3> <i>Chair: Carl Pixley</i><p> <a href="dacabs.htm#24_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/24_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 24.1 Efficient OBDD-Based Boolean Manipulation in CAD beyond Current Limits </a><br> <i>Jochen Bern, Christoph Meinel, Anna Slobodová</i><p> <a href="dacabs.htm#24_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/24_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 24.2 Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment </a><br> <i>Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan</i><p> <a href="dacabs.htm#24_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/24_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 24.3 Advanced Verification Techniques Based on Learning </a><br> <i>Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita</i><p> <a href="dacabs.htm#24_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/24_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 24.4 Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking </a><br> <i>E. M. Clarke, O. Grumberg, K. L. McMillan, X. Zhao</i><p> <hr> <h3>Session 25 <a href="dacabs.htm#sess25" name="sess25">Analog CAD</a></h3> <i>Chair: Jacob White</i><p> <a href="dacabs.htm#25_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/25_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 25.1 DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm* </a><br> <i>Wim Kruiskamp, Domine Leenaerts</i><p> <a href="dacabs.htm#25_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/25_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 25.2 Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels </a><br> <i>Ivan L. Wemple, Andrew T. Yang</i><p> <a href="dacabs.htm#25_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/25_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 25.3 Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits </a><br> <i>K. Lampaert, G. Gielen, W. Sansen</i><p> <a href="dacabs.htm#25_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/25_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 25.4 System-Level Design for Test of Fully Differential Analog Circuits </a><br> <i>Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman</i><p> <hr> <h3>Session 26 <a href="dacabs.htm#sess26" name="sess26">Panel: DOS, Windows, UNIX: EDA and the OS Wars </a></h3> <i>Chair: Richard Goering</i><br> <i>Panelists: Brian Moran, David Orecchio, David Pellerin, Jim Plymale, Nigel Ross, Patrick Williams</i><p> <hr> <h3>Session 27 <a href="dacabs.htm#sess27" name="sess27">Software Analysis and Synthesis</a></h3> <i>Chair: Rajesh K. Gupta</i><p> <a href="dacabs.htm#27_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/27_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 27.1 Performance Analysis of Embedded Software Using Implicit Path Enumeration </a><br> <i>Yau-Tsun Steven Li, Sharad Malik</i><p> <a href="dacabs.htm#27_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/27_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 27.2Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems</a><br> <i>Pai Chou, Gaetano Borriello</i><p> <a href="dacabs.htm#27_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/27_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 27.3 Interfacing Incompatible Protocols Using Interface Process Generation </a><br> <i>Sanjiv Narayan, Daniel D. Gajski</i><p> <hr> <h3>Session 28 <a href="dacabs.htm#sess28" name="sess28">Electrical Simulation</a></h3> <i>Chair: Lawrence T. Pileggi</i><p> <a href="dacabs.htm#28_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/28_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 28.1 Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm* </a><br> <i>Peter Feldmann, R. W. Freund</i><p> <a href="dacabs.htm#28_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/28_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 28.2 Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods </a><br> <i>Ricardo Telichevesky, Kenneth S. Kundert, Jacob K. White</i><p> <a href="dacabs.htm#28_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/28_3scn.pdf"><img src="../../../../../icons/pdficon.gif"></a> 28.3 Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach </a><br> <i>Mike Chou, Tom Korsmeyer, Jacob White</i><p> <hr> <h3>Session 29 <a href="dacabs.htm#sess29" name="sess29">Optimization of Clock and Power Distribution</a></h3> <i>Chair: Jason Cong</i><p> <a href="dacabs.htm#29_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/29_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 29.1 Buffer Insertion and Sizing under Process Variations for Low Power Clock Distribution* </a><br> <i>Joe G. Xi, Wayne W.-M. Dai</i><p> <a href="dacabs.htm#29_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/29_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 29.2 Power Optimal Buffered Clock Tree Design </a><br> <i>Ashok Vittal, Malgorzata Marek-Sadowska</i><p> <a href="dacabs.htm#29_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/29_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 29.3 Power Distribution Topology Design </a><br> <i>Ashok Vittal, Malgorzata Marek-Sadowska</i><p> <a href="dacabs.htm#29_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/29_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 29.4 On the Bounded-Skew Clock and Steiner Routing Problems </a><br> <i>Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao</i><p> <hr> <h3>Session 30 <a href="dacabs.htm#sess30" name="sess30">Concurrent Engineering</a></h3> <i>Chair: Neil Weste</i><p> <a href="dacabs.htm#30_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/30_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 30.1 Benchmarking an Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems* </a><br> <i>Asim Smailagic, Daniel P. Siewiorek, Drew Anderson, Chris Kasabach, Tom Martin, John Stivoric</i><p> <a href="dacabs.htm#30_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/30_2scn.pdf"><img src="../../../../../icons/pdficon.gif"></a> 30.2 A Methodology for HW-SW Codesign in ATM </a><br> <i>Giovanni Mancini, Dave Yurach, Spiros Boucouris</i><p> <a href="dacabs.htm#30_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/30_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 30.3 Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation </a><br> <i>Allan Silburt, Ian Perryman, Janick Bergeron, Stacy Nichols, Mario Dufresne, Greg Ward</i><p> <hr> <h3>Session 31 <a href="dacabs.htm#sess31" name="sess31">Panel: The ESDA Landscape: Who Will Dominate?</a></h3> <i>Chair: Kurt Keutzer</i><br> <i>Panelists: Moshe Cohen, Dominique Genin, Joachim Kunkle, Jan Rabaey, James Rowson, Gary Smith </i><p> <hr> <h3>Session 32 <a href="dacabs.htm#sess32" name="sess32">Formal Verification of Arithmetic Circuits</a></h3> <i>Chair: Gary D. Hachtel</i><p> <a href="dacabs.htm#32_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/32_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 32.1 Verification of Arithmetic Circuits with Binary Moment Diagrams* </a><br> <i>Randal E. Bryant, Yirng-An Chen</i><p> <a href="dacabs.htm#32_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/32_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 32.2Residue BDD and Its Application to the Verification of Arithmetic Circuits </a><br> <i>Shinji Kimura</i><p> <a href="dacabs.htm#32_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/32_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 32.3 Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions </a><br> <i>Zheng Zhou, Wayne Burleson</i><p> <hr> <h3>Session 33 <a href="dacabs.htm#sess33" name="sess33">Routing for FPGAs</a></h3> <i>Chair: Stephen Brown</i><p> <a href="dacabs.htm#33_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/33_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 33.1 On Optimal Board-Level Routing for FPGA-Based Logic Emulation </a><br> <i>Wai-Kei Mak, D.F. Wong</i><p> <a href="dacabs.htm#33_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/33_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 33.2 A Performance and Routability Driven Router for FPGAs Considering Path Delays </a><br> <i>Yuh-Sheng Lee, Allen C.-H. Wu</i><p> <a href="dacabs.htm#33_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/33_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 33.3 New Performance-Driven FPGA Routing Algorithms </a><br> <i>Michael J. Alexander, Gabriel Robins</i><p> <a href="dacabs.htm#33_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/33_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 33.4 Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing </a><br> <i>Yu-Liang Wu, Malgorzata Marek-Sadowska</i><p> <a href="dacabs.htm#33_5"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/33_5.pdf"><img src="../../../../../icons/pdficon.gif"></a> 33.5 Effects of FPGA Architecture on FPGA Routing </a><br> <i>Stephen Trimberger</i><p> <hr> <h3>Session 34 <a href="dacabs.htm#sess34" name="sess34">EDA and the WWW</a></h3> <i>Chair: Sean Murphy</i><p> <a href="dacabs.htm#34_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/34_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 34.1 The Case for Design Using the World Wide Web </a><br> <i>Mário J. Silva, Randy H. Katz</i><p> <a href="dacabs.htm#34_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/34_2.pdf"><img src="../../../../../icons/pdficon.gif></a> Panel: The Impact of the World Wide Web on Electronic Design and EDA </a><br> <i>Panelists: Jeff Allison, Jeff Angwin, Bob Dahlberg, Steven Levitan, Rob Rodin, Alex Silbey </i><p> <hr> <h3>Session 35 <a href="dacabs.htm#sess35" name="sess35">Code Generation for Embedded Systems</a></h3> <i>Chair: Pierre Paulin</i><p> <a href="dacabs.htm#35_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/35_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 35.1 Synthesis of Software Programs for Embedded Control Applications </a><br> <i>Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich</i><p> <a href="dacabs.htm#35_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/35_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 35.2 Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores* </a><br> <i>Adwin H. Timmer, Marino T.J. Strik, Jef L. van Meerbergen, Jochen A.G. Jess</i><p> <a href="dacabs.htm#35_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/35_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 35.3 Code Optimization Techniques for Embedded DSP Microprocessors </a><br> <i>Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang</i><p> <a href="dacabs.htm#35_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/35_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 35.4 Retargetable Self-Test Program Generation Using Constraint Logic Programming </a><br> <i>Ulrich Bieker, Peter Marwedel</i><p> <hr> <h3>Session 36 <a href="dacabs.htm#sess36" name="sess36">Switching Activity and Power Analysis</a></h3> <i>Chair: Farid N. Najm</i><p> <a href="dacabs.htm#36_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/36_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 36.1 Tutorial: Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits </a><br> <i>Farid N. Najm</i><p> <a href="dacabs.htm#36_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/36_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 36.2 Accurate Estimation of Combinational Circuit Activity </a><br> <i>Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin</i><p> <a href="dacabs.htm#36_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/36_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 36.3 Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits </a><br> <i>Farid N. Najm, Michael Y. Zhang</i><p> <a href="dacabs.htm#36_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/36_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 36.4 Efficient Power Estimation for Highly Correlated Input Streams </a><br> <i>Radu Marculescu, Diana Marculescu, Massoud Pedram</i><p> <a href="dacabs.htm#36_5"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/36_5.pdf"><img src="../../../../../icons/pdficon.gif"></a> 36.5 Power Estimation in Sequential Circuits* </a><br> <i>Farid N. Najm, Shashank Goel, Ibrahim N. Hajj</i><p> <hr> <h3>Session 37 <a href="dacabs.htm#sess37" name="sess37">Combinational Logic Synthesis</a></h3> <i>Chair: Yosinori Watanabe</i><p> <a href="dacabs.htm#37_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/37_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 37.1 New Ideas for Solving Covering Problems </a><br> <i>Olivier Coudert, Jean Christophe Madre</i><p> <a href="dacabs.htm#37_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/37_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 37.2 Logic Synthesis for Engineering Change </a><br> <i>Chih-chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng</i><p> <a href="dacabs.htm#37_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/37_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 37.3 A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix </a><br> <i>Yuichi Nakamura, Takeshi Yoshimura</i><p> <a href="dacabs.htm#37_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/37_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 37.4 Multi-Level Logic Minimization Based on Multi-Signal Implications </a><br> <i>Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita</i><p> <a href="dacabs.htm#37_5"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/37_5.pdf"><img src="../../../../../icons/pdficon.gif"></a> 37.5 An Efficient Algorithm for Local Don'’t Care Sets Calculation </a><br> <i>Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng</i><p> <a href="dacabs.htm#37_6"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/37_6.pdf"><img src="../../../../../icons/pdficon.gif"></a> 37.6 Logic Clause Analysis for Delay Optimization </a><br> <i>Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich</i><p> <hr> <h3>Session 38 <a href="dacabs.htm#sess38" name="sess38">Panel: Deep Submicron Design Challenges</a></h3> <i>Chair: Mike Smith</i><br> <i>Panelists: David Gregory, Jim Hogan, Tsutomu Iio, George Janac, Bill McCaffrey, Scott Nogueira</i><p> <hr> <h3>Session 39 <a href="dacabs.htm#sess39" name="sess39">Complexity Measures for VHDL</a></h3> <i>Chair: Reinaldo A. Bergamaschi</i><p> <a href="dacabs.htm#39_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/39_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 39.1 Tutorial: Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? </a><br> <i>Reinaldo A. Bergamaschi</i><p> <a href="dacabs.htm#39_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/39_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 39.2 Information Models of VHDL </a><br> <i>Cristian A. Giumale, Hilary J. Kahn</i><p> <a href="dacabs.htm#39_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/39_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 39.3 Measures of Syntactic Complexity for Modeling Behavioral VHDL </a><br> <i>Neal S. Stollon, John D. Provence</i><p> <hr> <h3>Session 40 <a href="dacabs.htm#sess40" name="sess40">Timing Analysis and Optimization</a></h3> <i>Chair: Ibrahim N. Hajj</i><p> <a href="dacabs.htm#40_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/40_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 40.1 Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization</a><br> <i>Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi</i><p> <a href="dacabs.htm#40_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/40_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 40.2 An Algorithm for Incremental Timing Analysis </a><br> <i>Jin-fuw Lee, Donald T. Tang</i><p> <a href="dacabs.htm#40_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/40_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 40.3 An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells </a><br> <i>Alessandro Dal Fabbro, Bruno Franzini, Luigi Croce, Carlo Guardiani</i><p> <a href="dacabs.htm#40_4"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/40_4.pdf"><img src="../../../../../icons/pdficon.gif"></a> 40.4 Automatic Clock Abstraction from Sequential Circuits </a><br> <i>Samir Jain, Randal E. Bryant, Alok Jain</i><p> <hr> <h3>Session 41 <a href="dacabs.htm#sess41" name="sess41">Asynchronous Synthesis</a></h3> <i>Chair: Steve Nowick</i><p> <a href="dacabs.htm#41_1"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/41_1.pdf"><img src="../../../../../icons/pdficon.gif"></a> 41.1 Hierarchical Optimization of Asynchronous Circuits </a><br> <i>Bill Lin, Gjalt De Jong, Tilman Kolks</i><p> <a href="dacabs.htm#41_2"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/41_2.pdf"><img src="../../../../../icons/pdficon.gif"></a> 41.2 Externally Hazard-Free Implementations of Asynchronous Circuits </a><br> <i>Milton Sawasaki, Chantal Ykman-Couvreur, Bill Lin</i><p> <a href="dacabs.htm#41_3"><img src="../../../../../icons/absicon.gif"></a> <a href="../../pdffiles/41_3.pdf"><img src="../../../../../icons/pdficon.gif"></a> 41.3 A Design and Validation System for Asynchronous Circuits </a><br> <i>Peter Vanbekbergen, Albert Wang, Kurt Keutzer</i><p> </body> </html>