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<b> [ <a href="authorix.htm">Author Index</a> ]
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<h1>TABLE OF CONTENTS EURODAC'94</h1>
<a href="../../pdffiles/ed94welc.pdf">Welcome Address of the General Chair</a><br>
<i>Jean Mermet, Université J. Fourier, Grenoble, France</i><br>
<a href="../../pdffiles/ed94scom.pdf">Steering Committee Members EURO-DAC '94 with EURO-VHDL '94</a><br>
<a href="../../pdffiles/ed94dcom.pdf">Program Committee Members EURO-DAC '94</a><br>
<a href="../../pdffiles/ed94vcom.pdf">Program Committee Members EURO-VHDL '94</a><br>
<hr>
<h4>SESSION D-01 <a href="abstract.htm#sessd1">LOGIC AND FPGA SYNTHESIS</a></h4>
<i>Chair: U.G. Baitinger, IPVR University of Stuttgart, Germany</i><p>
<a href="abstract.htm#d01_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d01_1.pdf">
D01.1 Fast OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions</a><br>
<i>Rolf Drechsler, Bernd Becker, Michael Theobald</i><p>
<a href="abstract.htm#d01_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d01_2.pdf">
D01.2 Free Kronecker Decision Diagrams and their Application to Atmel 6000 Series FPGA Mapping</a><br>
<i>Marek A.Perkowski, Philip Ho</i><p>
<a href="abstract.htm#d01_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d01_3.pdf">
D01.3 Multilevel Optimization of Very High Complexity Circuits</a><br>
<i>Luc Burgun, N. Dictus, Alain Greiner, E. Prado Lopes, C. Sarwary</i><p>
<br>
<hr>
<h4>SESSION D-02 <a href="abstract.htm#sessd2">SYMBOLIC STATE SPACE EXPLORATION AND SYSTEM TIMING</a></h4>
<i>Chair: Luc Claesen, IMEC, Katholieke Universiteit Leuven, Belgium</i><p>
<a href="abstract.htm#d02_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d02_1.pdf">
D02.1 Symbolic Exploration of Large Circuits with Enhanced Forward/Backward Traversals</a><br>
<i>Gianpiero Cabodi, P. Camurati, Stefano Quer</i><p>
<a href="abstract.htm#d02_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d02_2.pdf">
D02.2 Extended Timing Diagrams as a Specification Language</a><br>
<i>Stefan Lenk</i><p>
<a href="abstract.htm#d02_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d02_3.pdf">
D02.3 Efficient Algorithms for Interface Timing Verification</a><br>
<i>Ti-Yen Yen, Wayne Wolf, Al Casavant, Alex Ishii</i><p>
<hr>
<h4>SESSION D-03 <a href="abstract.htm#sessd3">TRANSISTOR LEVEL LAYOUT OPTIMIZATION</a></h4>
<i>Chair: Frank Johannes, Technical University of Munich, Germany</i><p>
<a href="abstract.htm#d03_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d03_1.pdf">
D03.1 A Unified Discrete Gate Sizing/Cell Library Optimization Method for Design and Analysis of Delay Minimized CMOS and BiCMOS Circuits</a><br>
<i>Kerry S. Lowe, P. Glenn Gulak</i><p>
<a href="abstract.htm#d03_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d03_2.pdf">
D03.2 Layout Optimization of Planar CMOS Cells Regarding Width-to-Height Trade-Off</a><br>
<i>Markus R. Theißinger, Ronald D. Hindmarsh</i><p>
D03.3 A Sequence Graph based Transistor Chaining Algorithm for Planar CMOS Cells</a><br>
<i>Oskar Anton, Karol Doerffer, Dieter Mlynski (no paper submitted)</i><p>
<a href="abstract.htm#d03_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d03_4.pdf">
D03.4 Automatic Layout Generation for CMOS Analog Transistors</a><br>
<i>H. Mathias, J. Berger-Toussan, F. Gaffiot, L. Hébrard, G. Jacquemod, Michel Le Helley</i><p>
<hr>
<h4>SESSION D-04 <a href="abstract.htm#sessd4">SPECIFIC CAD FOR FPGA AND CPLD DESIGN (PANEL)</a></h4>
<i>Chair: Gabrielle Saucier, Institut National de Polytechnique de Grenoble, France</i><p>
Panelists: <i>A. Biddle, Actel, Sunnyvale, CA, USA; D. Kohlmeier, Data I/O, Redmond, WA, USA;
A. Ditzinger, ISDATA, Karlsruhe, Germany; N. Toon, Altera, Marlow, United Kingdom</i><p>
<hr>
<h4>SESSION D-05 <a href="abstract.htm#sessd5">CODESIGN ARCHITECTURES</a></h4>
<i>Chair: Jørgen Staunstrup, Technical University of Denmark, Lyngby, Denmark</i><p>
<a href="abstract.htm#d05_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d05_1.pdf">
D05.1 A Prototyping Environment for Control-Oriented HW/SW Systems using State-Charts, Activity-Charts and FPGA's</a><br>
<i>Klaus Buchenrieder, Christian Veith</i><p>
<a href="abstract.htm#d05_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d05_2.pdf">
D05.2 A Performance Evaluator for Parameterized ASIC Architectures</a><br>
<i>Jie Gong, Daniel D. Gajski, Alex Nicolau</i><p>
<a href="abstract.htm#d05_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d05_3.pdf">
D05.3 Hardware-Software-Codesign of Application Specific Microcontrollers with the ASM Environment</a><br>
<i>A. Both, B. Biermann, R. Lerch, Y. Manoli, K. Sievert</i><p>
<a href="abstract.htm#d05_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d05_4.pdf">
D05.4 A Hardware Environment for Prototyping and Partitioning Based on Multiple FPGAs</a><br>
<i>Marc Wendling, Wolfgang Rosenstiel</i><p>
<hr>
<h4>SESSION D-06 <a href="abstract.htm#sessd6">DATA PATH AND CONTROL SYNTHESIS</a></h4>
<i>Chair: Nikil Dutt, University of California at Irvine, CA, USA</i><p>
<a href="abstract.htm#d06_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d06_1.pdf">
D06.1 GSA: Scheduling and Allocation Using Genetic Algorithm</a><br>
<i>Ali Shahid, Muhammed S. T. Benten, Sadiq M. Sait</i><p>
<a href="abstract.htm#d06_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d06_2.pdf">
D06.2 OSCAR: Optimum Simultaneous Scheduling, Allocation and Resource Binding based on Integer Programming</a><br>
<i>Birger Landwehr, Peter Marwedel, Rainer Dömer</i><p>
<a href="abstract.htm#d06_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d06_3.pdf">
D06.3 Parallel Controller Synthesis from a Petri Net Specification</a><br>
<i>Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul, Marian Adamski</i><p>
<hr>
<h4>SESSION D-07 <a href="abstract.htm#sessd7">SIMULATION OF MIXED SYSTEMS</a></h4>
<i>Chair: K.-L. Paap, GMD Gesellschaft für Mathematik und Datenverarbeitung, St. Augustin, Germany</i><p>
<a href="abstract.htm#d07_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d07_1.pdf">
D07.1 Parallel Algorithms for the Simulation of Lossy Transmission Lines</a><br>
<i>W. Rissiek, O. Rethmeier, H. Holzheuer</i><p>
<a href="abstract.htm#d07_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d07_2.pdf">
D07.2 Mixed Electrical-Thermal and Electrical-Mechanical Simulation of Electromechatronic Systems using PSPICE</a><br>
<i>Konstantin O. Petrosjanc, Peter P. Maltcev</i><p>
<a href="abstract.htm#d07_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d07_3.pdf">
D07.3 TRICAP-A Three Dimensional Capacitance Solver for Arbitrarily Shaped Conductors on Printed Circuit Boards and VLSI Interconnections</a><br>
<i>Matthias Tröscher, Hans Hartmann, Georg Klein, Andreas Plettner</i><p>
<a href="abstract.htm#d07_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d07_4.pdf">
D07.4 Advanced Simulation and Modeling Techniques for Hardware Quality Verification of Digital Systems</a><br>
<i>S. Forno, Stephen Rochel</i><p>
<hr>
<h4>SESSION D-08 <a href="abstract.htm#sessd8">SYSTEM AND CONCURRENT DESIGN</a></h4>
<i>Chair: Hans van Nielen, Philips Semiconductors, Nijmegen, The Netherlands</i><p>
<a href="abstract.htm#d08_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d08_1.pdf">
D08.1 OPERAS in a DSP CAD Environment</a><br>
<i>Gerard K. Yeh, Kallol Bagchi, Jim B. Burr, Allen M. Peterson</i><p>
<a href="abstract.htm#d08_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d08_2.pdf">
D08.2 Logic Synthesis for Reliability-An Early Start to Controlling Electromigration and Hot Carrier Effects</a><br>
<i>Kaushik Roy, Sharat Prasad</i><p>
D08.3 Automating the Concurrent Engineering Environment-A Five-Phase Approach</a><br>
<i>Donald E. Carter (no paper submitted)</i><p>
<hr>
<h4>SESSION D-09 <a href="abstract.htm#sessd9">SYSTEM AND INSTRUCTION SET DESIGN</a></h4>
<i>Chair: Ahmed A. Jerraya, INPG/TIMA, Grenoble, France</i><p>
<a href="abstract.htm#d09_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d09_1.pdf">
D09.1 100-hour Design Cycle: A Test Case</a><br>
<i>Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung</i><p>
<a href="abstract.htm#d09_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d09_2.pdf">
D09.2 A Tool for Processor Instruction Set Design</a><br>
<i>Bruce K. Holmer</i><p>
<a href="abstract.htm#d09_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d09_3.pdf">
D09.3 Instruction Set Extraction from Programmable Structures</a><br>
<i>Peter Marwedel, Rainer Leupers</i><p>
<hr>
<h4>SESSION D-10 <a href="abstract.htm#sessd10">NEW TECHNIQUES IN ANALOG MODELING AND SIMULATION</a></h4>
<i>Chair: Jacques Benkoski, EUREPIC, Gières, France</i><p>
<a href="abstract.htm#d10_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d10_1.pdf">
D10.1 Optimal Equivalent Circuits for Interconnect Delay Calculations Using Moments</a><br>
<i>Sudhakar Muddu, Andrew B. Kahng</i><p>
<a href="abstract.htm#d10_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d10_2.pdf">
D10.2 Efficient Linear Circuit Analysis by Padé Approximation via the Lanczos Process</a><br>
<i>Peter Feldmann, Roland W. Freund</i><p>
<a href="abstract.htm#d10_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d10_3.pdf">
D10.3 Multilevel Generalization of Relaxation Algorithms for Circuit Simulation</a><br>
<i>Vladimir B. Dmitriyev Zdorov</i><p>
<a href="abstract.htm#d10_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d10_4.pdf">
D10.4 MOS VLSI Circuit Simulation by Hardware Accelerator Using Semi-Natural Models</a><br>
<i>Victor V. Denisenko</i><p>
<hr>
<h4>SESSION D-11 <a href="abstract.htm#sessd11">TOOL INTEROPERABILITY</a></h4>
<i>Chair: Jim Heaton, ICL, Manchester, United Kingdom</i><p>
<a href="abstract.htm#d11_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d11_1.pdf">
D11.1 A Flexible Access Control Mechanism for CAD Frameworks</a><br>
<i>A.J. van der Hoeven, Olav ten Bosch, Rene van Leuken, Pieter van der Wolf</i><p>
<a href="abstract.htm#d11_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d11_2.pdf">
D11.2 A Tightly Coupled Approach to Design and Data Management</a><br>
<i>Flávio R. Wagner, Lia G. Golendziner, Miguel R. Fornari</i><p>
<a href="abstract.htm#d11_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d11_3.pdf">
D11.3 Integrating CAD Tools into a Framework Environment Using a Flexible and Adaptable Procedural Interface</a><br>
<i>Nick Filer, Michael Brown, Zahir Moosa</i><p>
<a href="abstract.htm#d11_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d11_4.pdf">
D11.4 Design Tool Encapsulation-All Problems Solved?</a><br>
<i>Olav Schettler</i><p>
<hr>
<h4>SESSION D-12 <a href="abstract.htm#sessd12">HW/SW PARTITIONING</a></h4>
<i>Chair: Klaus Buchenrieder, Siemens AG, München, Germany</i><p>
<a href="abstract.htm#d12_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d12_1.pdf">
D12.1 A Binary-Constraint Search Algorithm for Minimizing Hardware During Hardware/Software Partitioning</a><br>
<i>Frank Vahid, Daniel D. Gajski, Jie Gong</i><p>
<a href="abstract.htm#d12_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d12_2.pdf">
D12.2 A Method for Partitioning UNITY Language in Hardware and Software</a><br>
<i>Xun Xiong, Edna Barros, Wolfgang Rosenstiel</i><p>
<a href="abstract.htm#d12_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d12_3.pdf">
D12.3 Hardware/Software Partitioning and Minimizing Memory Interface Traffic</a><br>
<i>Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen</i><p>
<hr>
<h4>SESSION D-13 <a href="abstract.htm#sessd13">SELF-TESTING AND SELF-CHECKING</a></h4>
<i>Chair: Franc Brglez, NCSU, Research Triangle Park, NC, USA</i><p>
<a href="abstract.htm#d13_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d13_1scn.pdf">
D13.1 Reliability Study of Combinational Circuits</a><br>
<i>Edgar Holmann, Ivan R. Linscott, G. Leonard Tyler</i><p>
<a href="abstract.htm#d13_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d13_2.pdf">
D13.2 Test Pattern Generation Hardware Motivated by Pseudo-Exhaustive Test Techniques</a><br>
<i>Arno B. Kunzmann</i><p>
<a href="abstract.htm#d13_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d13_3.pdf">
D13.3 An Experimental Analysis of the Effectiveness of the Circular Self-Test Path Technique</a><br>
<i>Paolo Prinetto, Fulvio Corno, Sonza Reorda</i><p>
<a href="abstract.htm#d13_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d13_4.pdf">
D13.4 Design Automation of Self Checking Circuits</a><br>
<i>S.M. Kia, Sri Parameswaran</i><p>
<hr>
<h4>SESSION D-14 <a href="abstract.htm#sessd14">PARTITIONING, PLACEMENT, AND ROUTING FOR FPGA</a></h4>
<i>Chair: Bryan Preas, Xerox PARC, Palo Alto, CA, USA</i><p>
<a href="abstract.htm#d14_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d14_1.pdf">
D14.1 An Architecture-Independent Approach to FPGA Routing Based on Multi-Weighted Graphs</a><br>
<i>Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins</i><p>
<a href="abstract.htm#d14_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d14_2.pdf">
D14.2 Algorithms for a Switch Module Routing Problem</a><br>
<i>Shashidhar Thakur, D.F. Wong, S. Muthukrishnan</i><p>
<a href="abstract.htm#d14_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d14_3.pdf">
D14.3 A Unified Cost Model for Min-Cut Partitioning with Replication Applied to Optimization of Large Heterogeneous FPGA Partitions</a><br>
<i>Roman Kuznar, Baldomir Zajc, Franc Brglez</i><p>
<a href="abstract.htm#d14_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d14_4.pdf">
D14.4 A Delay-Driven FPGA Placement Algorithm</a><br>
<i>Srilata Raman, C.L. Liu, Larry G. Jones</i><p>
<hr>
<h4>SESSION D-15 <a href="abstract.htm#sessd15">APPLICATION OF CAD ALGORITHMS IN NON-ELECTRONIC DOMAINS (PANEL)</a></h4>
<i>Chair: Gerry Musgrave, Brunel University, Uxbridge, United Kingdom</i><p>
Panelists:
<i> Björn Schieffer, Universität des Saarlandes, Saarbrücken, Germany;
Ulrich Lauther, Siemens AG, Munich, Germany; Thomas Lengauer, GMD Uni Bonn, Germany;
Daniel Schweikert, AutoGateLogic Inc., Fremont, CA, USA</i>
<hr>
<h4>SESSION D-16 <a href="abstract.htm#sessd16">FORMAL VERIFICATION</a></h4>
<i>Chair: Luc Claesen, IMEC, Leuven, Belgium</i><p>
<a href="abstract.htm#d16_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d16_1.pdf">
D16.1 Formal Verification of Pipeline Conflicts in RISC Processors</a><br>
<i>Ramayya Kumar, Sofiène Tahar</i><p>
<a href="abstract.htm#d16_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d16_2.pdf">
D16.2 An Automatically Verified Generalized Multifunction Arithmetic Pipeline</a><br>
<i>Matthias Mutz</i><p>
<a href="abstract.htm#d16_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d16_3.pdf">
D16.3 Formal Specification and Simulation of Instruction-Level Parallelism</a><br>
<i>Edwin A. Harcourt, Jon Mauney, Todd Cook</i><p>
<a href="abstract.htm#d16_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d16_4.pdf">
D16.4 An Efficient Verification Algorithm for Parallel Controllers</a><br>
<i>Krzystof Bilinski, Erik L. Dagless, Jonathan Saul, Janusz Szajna</i><p>
<hr>
<h4>SESSION D-17 <a href="abstract.htm#sessd17">ATPG FOR DELAY FAULTS</a></h4>
<i>Chair: Kurt Antreich, Technical University of Munich, Germany</i><p>
<a href="abstract.htm#d17_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d17_1.pdf">
D17.1 Tests for Path Delay Faults vs. Tests for Gate Delay Faults: How Different They Are</a><br>
<i>Andrzej Kraâniewski, Leszek B. Wroáski</i><p>
<a href="abstract.htm#d17_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d17_2.pdf">
D17.2 RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults</a><br>
<i>Karl Fuchs, Michael Pabst, Torsten Rössel</i><p>
<a href="abstract.htm#d17_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d17_3.pdf">
D17.3 BiTeS: A BDD based Test Pattern Generator for Strong Robust Path Delay Faults</a><br>
<i>Rolf Drechsler</i><p>
<a href="abstract.htm#d17_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d17_4.pdf">
D17.4 Testing Redundant Asynchronous Circuits by Variable Phase Splitting</a><br>
<i>Luciano Lavagno, Antonio Lioy, Michael Kishinevsky</i><p>
<hr>
<h4>SESSION D-18 <a href="abstract.htm#sessd18">KNOWLEDGE BASED APPROACHES</a></h4>
<i>Chair: Franz J. Rammig, University, GH Paderborn, Germany</i><p>
<a href="abstract.htm#d18_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d18_1.pdf">
D18.1 Re-engineering Hardware Specifications by Exploiting Design Semantics</a><br>
<i>Salvador Mir, Nick Filer</i><p>
<a href="abstract.htm#d18_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d18_2.pdf">
D18.2 The Use of Semantic Information for Control of a Complex Routing Tool</a><br>
<i>Michael Brown, Nick Filer, Zahir Moosa</i><p>
<a href="abstract.htm#d18_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d18_3.pdf">
D18.3 A New Knowledge-Based Design Manager Assistant for CAD Frameworks</a><br>
<i>F. Moreno, J. Meneses</i><p>
<a href="abstract.htm#d18_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d18_4.pdf">
D18.4 The Use of Single and Multiple Seed Architectures with a Natural Based Micro-Architecture Exploration Algorithm</a><br>
<i>Chris J. Rouse, Alison J. Carter</i><p>
<hr>
<h4>SESSION D-19 <a href="abstract.htm#sessd19">TIMING VERIFICATION AND LOGIC SIMULATION</a></h4>
<i>Chair: John Forrest, UMIST, Manchester, United Kingdom</i><p>
<a href="abstract.htm#d19_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d19_1.pdf">
D19.1 Compiled-Code-Based Simulation with Timing Verification</a><br>
<i>Winfried Hahn, Andreas Hagerer, C. Herrmann</i><p>
<a href="abstract.htm#d19_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d19_2.pdf">
D19.2 A Portable and Extendible Testbed for Distributed Logic Simulation</a><br>
<i>Peter Luksch</i><p>
<a href="abstract.htm#d19_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d19_3.pdf">
D19.3 Gate-Level Timing Verification Using Waveform Narrowing</a><br>
<i>Jindrich Zejda, Eduard Cerny</i><p>
<a href="abstract.htm#d19_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d19_4.pdf">
D19.4 Exact Path Sensitization in Timing Analysis</a><br>
<i>R. Peset Llopis</i><p>
<hr>
<h4>SESSION D-20 <a href="abstract.htm#sessd20">ESTIMATION AND SYNTHESIS</a></h4>
<i>Chair: Manfred Glesner, Darmstadt University of Technology, Germany</i><p>
<a href="abstract.htm#d20_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d20_1.pdf">
D20.1 A New Power Estimation Technique with Application to Decomposition of Boolean Functions for Low Power</a><br>
<i>Peter H. Schneider, Kurt J. Antreich, Ulf Schlichtmann</i><p>
<a href="abstract.htm#d20_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d20_2.pdf">
D20.2 A New Technique for Exploiting Regularity in Data Path Synthesis</a><br>
<i>C.Y. Roger Chen, Mohammed Aloqeely</i><p>
<a href="abstract.htm#d20_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d20_3.pdf">
D20.3 A Component Selection Algorithm for DSP Pipelines</a><br>
<i>Smita Bakshi, Daniel D. Gajski</i><p>
<hr>
<h4>SESSION D-21 <a href="abstract.htm#sessd21">THERMAL AND EMC EFFECTS ON PCBS</a></h4>
<i>Chair: Karl-Heinz Diener, FhG-IIS, Dresden, Germany</i><p>
<a href="abstract.htm#d21_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d21_1.pdf">
D21.1 Fast Simulation Methods for the Detection of Reflection and Crosstalk Effects During the Design of Complex Printed Circuit Boards</a><br>
<i>E. Griese, J. Schrage, M. Vogt</i><p>
<a href="abstract.htm#d21_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d21_2.pdf">
D21.2 Design Support of Printed Circuit Boards Concerning Radiation and Irradiation Effects (EMI) Using an Extended EMC-Workbench</a><br>
<i>Stefan Öing, Werner John</i><p>
<a href="abstract.htm#d21_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d21_3.pdf">
D21.3 Overall Thermal Simulation of Electronic Equipment</a><br>
<i>Jean-Louis Blanchard, Jean-Michel Morelle</i><p>
<hr>
<h4>SESSION D-22 <a href="abstract.htm#sessd22">CHIP LEVEL ROUTING</a></h4>
<i>Chair: Tokinori Kozawa, Hitachi Ltd., Tokyo, Japan</i><p>
<a href="abstract.htm#d22_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d22_1.pdf">
D22.1 A Macro-Cell Global Router Based on Two Genetic Algorithms</a><br>
<i>Henrik Esbensen</i><p>
<a href="abstract.htm#d22_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d22_2.pdf">
D22.2 An Application of Simulated Annealing to Maze Routing</a><br>
<i>Zahir Moosa, Michael Brown, Douglas Edwards</i><p>
<a href="abstract.htm#d22_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d22_3.pdf">
D22.3 Planar-DME: Improved Planar Zero-Skew Clock Routing with Minimum Pathlength Delay</a><br>
<i>C.W. Albert Tsao, Andrew B. Kahng</i><p>
<hr>
<h4>SESSION D-23 <a href="abstract.htm#sessd23">ASYNCHRONOUS AND ANALOG SYNTHESIS</a></h4>
<i>Chair: Jørgan Staunstrup, Technical University of Denmark, Lyngby, Denmark</i><p>
<a href="abstract.htm#d23_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/d23_1.pdf">
D23.1 A General State Graph Transformation Framework for Asynchronous Synthesis</a><br>
<i>Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekbergen</i><p>
<a href="abstract.htm#d23_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/d23_2.pdf">
D23.2 Evaluation of Function Blocks for Asynchronous Design</a><br>
<i>Christian D. Nielsen</i><p>
<a href="abstract.htm#d23_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/d23_3.pdf">
D23.3 Modeling and Synthesis of Timed Asynchronous Circuits</a><br>
<i>Peter Vanbekbergen, Gert Goossens, Bill Lin</i><p>
<a href="abstract.htm#d23_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/d23_4.pdf">
D23.4 Application Independent Hierarchical Synthesis Methodology for Analogue Circuits</a><br>
<i>Reimund Wittmann, Bedrich Hosticka, Michael Schanz, Werner Schardein, Stefan Kern, Reinhold Vahrmann</i><p>
<hr>
<h4>SESSION V-01 <a href="abstract.htm#sessv1">MODELING</a></h4>
<i>Chair: Wolfang Nebel, Carl-von-Ossietzky Universität, Oldenburg, Germany</i><p>
<a href="abstract.htm#v01_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v01_1.pdf">
V01.1 Generating VHDL Models from Natural Language Descriptions</a><br>
<i>Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik, Alexander J. Honcharik</i><p>
<a href="abstract.htm#v01_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v01_2.pdf">
V01.2 Non-Reversible VHDL Source-Source Encryption</a><br>
<i>Kevin O'Brien, Serge Maginot</i><p>
<a href="abstract.htm#v01_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v01_3.pdf">
V01.3 Modeling Shared Variables in VHDL</a><br>
<i>Jan Madsen, Jens P. Brage</i><p>
<a href="abstract.htm#v01_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/v01_4.pdf">
V01.4 A VHDL-Based Bus Model for Multi-PCB System Design</a><br>
<i>Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuominen</i><p>
<hr>
<h4>SESSION V-02 <a href="abstract.htm#sessv2">SEMANTIC MODELS FOR VHDL</a></h4>
<i>Chair: Serafin Olcoz, TGI S.A., Madrid, Spain</i><p>
<a href="abstract.htm#v02_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v02_1.pdf">
V02.1 The Semantics of Behavioral VHDL '93 Descriptions</a><br>
<i>Wolfgang Müller, Egon Börger, Uwe Glässer</i><p>
<a href="abstract.htm#v02_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v02_2.pdf">
V02.2 A Process Algebra Interpretation of a Verification Oriented Overlanguage of VHDL</a><br>
<i>Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto</i><p>
<a href="abstract.htm#v02_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v02_3.pdf">
V02.3 Proof Theory and a Validation Condition Generator for VHDL</a><br>
<i>Luis Sánchez, Peter T. Breuer, Carlos Delgado-Kloos</i><p>
<hr>
<h4>SESSION V-03 <a href="abstract.htm#sessv3">DESIGN TECHNIQUES</a></h4>
<i>Chair: Franz J. Rammig, University - GH Paderborn, Germany</i><p>
<a href="abstract.htm#v03_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v03_1.pdf">
V03.1 Implementation of a SDH STM-N IC for B-ISDN Using VHDL Based Synthesis Tools</a><br>
<i>Juan Carlos Calderón, Enric Corominas, José M. Tapia, Lluis París</i><p>
<a href="abstract.htm#v03_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v03_2.pdf">
V03.2 VHDL and Cyclic Corrector Codes</a><br>
<i>France Mendez</i><p>
<a href="abstract.htm#v03_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v03_3.pdf">
V03.3 Generating Compilers for Generated Datapaths</a><br>
<i>Michael Held, Manfred Glesner</i><p>
<hr>
<h4>SESSION V-04 <a href="abstract.htm#sessv4">VHDL AND SYNTHESIS (I)</a></h4>
<i>Chair: Sabine März, Siemens AG, Munich, Germany</i><p>
<a href="abstract.htm#v04_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v04_1.pdf">
V04.1 Synthesis of VHDL Concurrent Processes</a><br>
<i>Petru Eles, Marius Minea, Krzysztof Kuchcinski, Zebo Peng</i><p>
<a href="abstract.htm#v04_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v04_2.pdf">
V04.2 Scheduling of Behavioral VHDL by Retiming Techniques</a><br>
<i>N. Wehn, J. Biesenack, Peter Duzy, T. Langmaier, M. Münch , Michael Pilsl, S. Rumler</i><p>
<a href="abstract.htm#v04_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v04_3.pdf">
V04.3 A Transformation for Integrating VHDL Behavioral Specification with Synthesis and Software Generation</a><br>
<i>Frank Vahid, Daniel D. Gajski, Sanjiv Narayan</i><p>
<hr>
<h4>SESSION V-05 <a href="abstract.htm#sessv5">WHY EXTEND VHDL TO ANALOG? (PANEL)</a></h4>
<i>Chair: Jean-Michel Bergé, CCI/MCC, Meylan, France</i><p>
Panelists:
<i>Ernst Christen, ANALOGY Inc., Beaverton, OR, USA; John Hines, US Air-Force, WPAFB, OH, USA;
Stanley J. Krolikoski, Compass Design Automation, Rochester, MN, USA; Eduard Moser, Robert Bosch GmbH, Stuttgart, Germany;
David Rhodes, US Army Research Laboratory/EPSD, Ft. Monmouth, NJ, USA; Jacques Rouillard, ESIM, Marseille, France</i><p>
<hr>
<h4>SESSION V-06 <a href="abstract.htm#sessv6">FROM VHDL TO FORMAL VERIFICATION</a></h4>
<i>Chair: Dominique Borrione, IMAG/ARTEMIS, Grenoble, France</i><p>
<a href="abstract.htm#v06_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v06_1.pdf">
V06.1 Formal Verification of Behavioural VHDL Specifications: A Case Study</a><br>
<i>Félix Nicoli, Laurence Pierre</i><p>
<a href="abstract.htm#v06_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v06_2.pdf">
V06.2 (V)HDL-based Verification of Heterogeneous Synchronous / Asynchronous Systems</a><br>
<i>Hans Eveking</i><p>
<a href="abstract.htm#v06_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v06_3scn.pdf">
V06.3 Petri Nets as Intermediate Representation between VHDL and Symbolic Transition Systems</a><br>
<i>Gert Döhmen</i><p>
<a href="abstract.htm#v06_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/v06_4.pdf">
V06.4 Computing Binary Decision Diagrams for VHDL Data Types</a><br>
<i>Ronald Herrmann, Hergen Pargmann</i><p>
<hr>
<h4>SESSION V-07 <a href="abstract.htm#sessv7">VHDL SIMULATION</a></h4>
<i>Chair: Jacques Rouillard, ESIM, Marseille, France</i><p>
<a href="abstract.htm#v07_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v07_1scn.pdf">
V07.1 Static Analysis for VHDL Model Evaluation</a><br>
<i>Mirella Mastretti, Alessandro Balboni, Mario Stefanoni</i><p>
<a href="abstract.htm#v07_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v07_2.pdf">
V07.2 Automotive Databus Simulation Using VHDL</a><br>
<i>Karen Hale</i><p>
<a href="abstract.htm#v07_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v07_3.pdf">
V07.3 Distributed Simulation of Structural VHDL Netlists</a><br>
<i>Werner van Almsick, Wilfried Daehn, David B. Bernstein</i><p>
<a href="abstract.htm#v07_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/v07_4.pdf">
V07.4 A New Flexible VHDL Simulator</a><br>
<i>Arlet Ottens, Henk Corporaal, Wilco van Hoogstraeten</i><p>
<hr>
<h4>SESSION V-08 <a href="abstract.htm#sessv8">VHDL AND SYNTHESIS (II)</a></h4>
<i>Chair: Eugenio Villar, University of Cantabria, Santander, Spain</i><p>
<a href="abstract.htm#v08_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v08_1.pdf">
V08.1 The Role of VHDL within the TOSCA Hardware/Software Codesign Framework</a><br>
<i>Donatella Sciuto,Stefano Antoniazzi, Alessandro Balboni, Settimo Milanese, William Fornaciari</i><p>
<a href="abstract.htm#v08_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v08_2.pdf">
V08.2 Timing Preserving Interface Transformations for the Synthesis of Behavioural VHDL</a><br>
<i>P. Gutberlet, Wolfgang Rosenstiel</i><p>
<a href="abstract.htm#v08_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v08_3.pdf">
V08.3 Protocol Merging: A VHDL-Based Method for Clock Cycle Minimizing and Protocol Preserving Scheduling of IO-Operations</a><br>
<i>Wolfgang Ecker, Manfred Glesner, Andreas Vombach</i><p>
<hr>
<h4>SESSION V-09 <a href="abstract.htm#sessv9">TEST GENERATION AND FAULT SIMULATION</a></h4>
<i>Chair: John Hillawi, DA Solutions, Gosport, United Kingdom</i><p>
<a href="abstract.htm#v09_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/v09_1.pdf">
V09.1 Speeding up Test Pattern Generation from Behavioral VHDL Descriptions Containing Several Processes</a><br>
<i>L. Vandeventer, J.F. Santucci</i><p>
<a href="abstract.htm#v09_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/v09_2.pdf">
V09.2 Algorithms for Behavioral Test Pattern Generation from HDL Circuit Descriptions Containing Loop Language Constructs</a><br>
<i>L. Vandeventer, J.F. Santucci</i><p>
<a href="abstract.htm#v09_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/v09_3.pdf">
V09.3 Testability Analysis and Improvement from VHDL Behavioral Specifications</a><br>
<i>Xinli Gu, Krzyztof Kuchcinski, Zebo Peng</i><p>
<a href="abstract.htm#v09_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/v09_4.pdf">
V09.4 VHDL Switch Level Fault Simulation</a><br>
<i>Christopher A. Ryan, Joseph G. Tront</i><p>
<hr>
<h4>SESSION V-10 <a href="abstract.htm#sessv10">FORMAL SEMANTICS OF VHDL: PRACTICAL NEEDS OR ACADEMIC PLEASURE ? (PANEL)</a></h4>
<i>Chair: Franz J. Rammig, CADLAB, Paderborn, Germany</i><p>
Panelists:
<i>E. Berger, Universita di Pisa, Italy; Dominique Borrione, IMAG/ARTEMIS, Grenoble, France;
Stanley J. Krolikoski, Compass Design Automation, Rochester, MN, USA; Gerry Musgrave, AHL Abstract Hardware Ltd., Uxbridge, United Kingdom;
Carlos Delgado-Kloos, Universidad Polytecnica de Madrid, Spain; M. Payer, Siemens AG, Munich, Germany</i><p>
<hr>
<h4>User Session (Track 4) <a href="abstract.htm#sessu4">DESIGN METHODOLOGIES (USER SESSION)</a></h4>
<i>Chair: Leo Cloetens, Alcatel Bell Telephone, Belgium</i><p>
<a href="abstract.htm#u04_1"><img src="psicon.gif"></a>
<a href="../../pdffiles/u04_1.pdf">
ASIC Synthesis of a Flexible 80 Mbit/s Reed-Solomon Codec with DSP Station</a><br>
<i>Koen Van Nieuwenhove, Kjell Cools, D. Derisch, Dominique Genin, Ivo Bolsens, Serge Vernalde, Kim Chansik, Bang W. Lee, Oh Younguk</i><p>
<a href="abstract.htm#u04_2"><img src="psicon.gif"></a>
<a href="../../pdffiles/u04_2.pdf">
A VHDL-based Design Methodology: The Design Experience of a High Performance ASIC Chip</a><br>
<i>Maurizio Valle, Daniele Caviglia, Marco Cornero, Giovanni Nateri, Luciano Briozzo</i><p>
<a href="abstract.htm#u04_3"><img src="psicon.gif"></a>
<a href="../../pdffiles/u04_3scn.pdf">
SYNOPA: An Automated Synthesizer for CMOS Operational Amplifiers</a><br>
<i>Daniel Clavelier, Bernard Hennion, Christopher Nilson</i><p>
<a href="abstract.htm#u04_4"><img src="psicon.gif"></a>
<a href="../../pdffiles/u04_4scn.pdf">
Using C to Write Portable CMOS VLSI Module Generators</a><br>
<i>Alain Greiner, Frédéric Pétrot</i><p>
<a href="abstract.htm#u04_5"><img src="psicon.gif"></a>
<a href="../../pdffiles/u04_5.pdf">
Rapid Prototyping for DSP Circuits using High Level Design Tools</a><br>
<i>Stefan Tamme</i><p>
<a href="abstract.htm#u04_6"><img src="psicon.gif"></a>
<a href="../../pdffiles/u04_6.pdf">
CAD Education and Science in Ukraine after Perestroika</a><br>
<i>Alexander Y. Tetelbaum</i><p>
<hr>
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