";
    // print_r ($auth_object);
    // print "

EECS 31L/CSE 31L: Lab 1 (Winter 2012)

Objective

In this assignment, you will design a small digital circuit, called MuseumAlarm. A museum has four rooms, each with a motion sensor (m0, m1, m2, and m3) that outputs 1 when motion in the room is detected. At night, the only person in the museum is one security guard who walks from room to room. Create a combinatorial circuit that sounds an alarm ( by setting an output A to 1) if motion is ever detected in more than one room at a time (i.e., in two or three rooms), meaning there must be one or more intruders in the museum.

The purpose of this assignment is threefold:

1. To refresh your memory on combinatorial logic design that you have learned in digital design class (see video: Logic Design),
2. To get used to Xilinx design and simulation tools (see video Simulation Principles and 31L and Xilinx tutorial videos),
3. To learn some VHDL basics (see Lab1 videos: Logic Gates, Logic Components, and Hierarchical Components).

Procedure

This lab assignment requires you to translate a design specification in English language into a digital design consisting of gates from the given library. You are asked to develop a behavioral (functional) and structural (netlist) model and compare them with simulation (see Lab 1 videos for definition of behavioral and structural models).

1. Create a truth table for the MuseumAlarm from the English description above;
2. Derive a minimal sum-of-products or product-of-sums Boolean equation;
3. Modify Boolean equation for implementation with 3-input NAND gates using Boolean algebra rules;
4. Optimize the equation for minimal input-output delay with 3-input NAND gates (1.8ns delay each);
5. Create VHDL behavioral description for MuseumAlarm;
6. Create VHDL structural description for MuseumAlarm;
7. Create test bench for MuseumAlarm;
8. Simulate your design and report the input-output delay. Repeat until results match all the cases in the truth table.

Deliverable

Upload your VHDL file to drop box (EECS31/CSE31L>31Lab1>Assignment submission).

File name should be "Lab1b_studentID.vhd" and "Lab1s_studentID.vhd".

Example:

If your student ID is "12345678", then you should submit "Lab1b_12345678.vhd" for your behavioral model and "Lab1s_12345678.vhd" for your structural model.

Use the following templates:

Notes:

1. The templates include declaration of the entities that you have to design. You have to add the behavior and structural architecture.
2. Do NOT change the names of the entities and ports in the templates.

Template 1: Lab1b_studentID.vhd

----------------------------------------------------------------------
-- EECS31L/CSE31L Assignment1
-- MuseumAlarm Behavioral Model
----------------------------------------------------------------------
-- Student First Name : Your First Name
-- Student Last Name : Your Last Name
-- Student ID : Your Student ID
----------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY MuseumAlarm_behav IS
   PORT (m0, m1, m2, m3: IN std_logic;
         A: OUT std_logic);
END MuseumAlarm_behav;

ARCHITECTURE Behav OF MuseumAlarm_behav IS


-- add your code here

END Behav;

Template 2: Lab1s_studentID.vhd

----------------------------------------------------------------------
-- EECS31L/CSE31L Assignment1
-- MuseumAlarm Structural Model
----------------------------------------------------------------------
-- Student First Name : Your First Name
-- Student Last Name : Your Last Name
-- Student ID : Your Student ID
----------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY NAND3 IS
   PORT (x: IN std_logic;
         y: IN std_logic;
         z: IN std_logic;
         F: OUT std_logic);
END NAND3;  

ARCHITECTURE behav OF NAND3 IS
BEGIN
   PROCESS(x, y, z)
   BEGIN
      F <= NOT (x AND y AND z) AFTER 1.8 ns; 
   END PROCESS;
END behav;
----------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MuseumAlarm_struct IS
   PORT (m0, m1, m2, m3: IN std_logic;
         A: OUT std_logic);
END MuseumAlarm_struct;

ARCHITECTURE Struct OF MuseumAlarm_struct IS

-- add your code here

END Struct;

Due Date

Lab1B (Lab1S) due by 12:00 PM on:

January 20 (27), 2012

Early Submission Deadline

1 extra point for Lab1B, 1 extra point for Lab1S

Lab1B (Lab1S) due by 12:00 PM on:

January 13 (20), 2012