UCI Cadlab
Technical Reports 2006


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PDF TR-06-08

Eric James Johnson, Andreas Gerstlauer and Rainer Doemer,
"Efficient Debugging and Tracing of System Level Designs,"
CECS, UC Irvine, Technical Report CECS-TR-06-08, May 2006.

System Level Design Languages (SLDL) have been created to address the unique needs of system-on-a-chip (SOC) design. Among these needs are the ability to work from a specification model, perform architectural explorations, and refine the models to come up with a final model that may be synthesized into hardware and custom software components. The SpecC language in particular was designed with these goals in mind.

Prior to the work described here, the SpecC design environment consisted of a compiler, simulator, and EDA tools for exploring architectures and refining of models. Tools for debug and analysis of simulations were not widely available. We describe the design and implementation of new software APIs for debugging and new capabilities within the simulator for producing simulation logs, which can be used as debugging tools and for performing system architecture analysis. This work paves the way for more sophisticated analysis tools that hold the promise of providing designers with better feedback for performing system architecture explorations.

We also demonstrate that these new capabilities have been applied to real system designs including ARM Processor models, AMBA and CAN bus models, and an industrial-strength MP3 Audio Decoder design. Our results show that through the use of these capabilities, debugging time has decreased dramatically, thus allowing designers to finish their implementations in a more timely fashion.


PDF TR-06-06

Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer and Rainer Doemer,
"Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor,"
CECS, UC Irvine, Technical Report CECS-TR-06-06, May 2006.

System level design is one approach to tackle the complexity of designing a modern System-on-Chip. One major aspect is the capability of developing the system model irrespectable of the later occurring hardware software split, with the goal to develop both hardware and software seamlessly at the same time and to merge the traditionally separated development flows.

Hardware/software co-simulation is needed for an efficiently integrated design flow. Depending on the design phase, this co-simulation can be performed at different levels of abstraction. Early in the design phase, a very abstract simulation at the unpartitioned specification level yields fast functional results. On the other end, the cycle accurate simulation of RTL hardware and instruction set simulated software allows an accurate insight to the final system performance.

This report focuses on the software perspective of a co-design/co-simulation environment. In form of a case study, we address three major tasks necessary to build an integrated embedded software design flow: modeling of a processor core (including an instruction set simulator), porting of a RTOS to the selected processor core, and the embedded software generation that includes RTOS targeting of the generated code.

In particular, we have modeled a popular ARM core, the ARM7TDMI, at an abstract level, as well as on a cycle-accurate level using SWARM, an Instruction Set Simulator (ISS) for the ARM core. Furthermore, we have ported MicroC/OS-II, a Real-Time Operating System (RTOS), to run on top of the SWARM ISS. Finally, we implemented a software generation tool. It automatically synthesizes C code, targeted to the selected Real-Time Operating System (RTOS), from the refined design captured in the a system level design language.

We demonstrate our embedded software development flow by use of an automotive application. An example of anti-lock breaks uses a distributed architecture of sensors and actuators connected via a Controller Area Network (CAN). We undergo all steps of the design flow starting with the capturing of the specication model, down to validation of the implementation with an ISS based co-simulation. Our results show that the co-design/cosimulation environment is feasible. All refined models, including the ISS based cycle-accurate model, show a functional correct behavior.


Last update: May 22, 2006 by A. Gerstlauer (gerstl@cecs.uci.edu).