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This report describes the scheduling algorithm in RTL design methodology. The proposed scheduling algrorithm is based on resource constrained list scheduling, which considers the number of function units, storage units, busses and ports of storage units in each control step, and supports the pipelined/multicycle operations and storage units, such as pipelined register files and latched memory.

We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, waitfor, par, pipe, and try statements as they are introduced in SpecC. We present our definition in form of distributed Abstract State Machine (ASM) rules reflecting the specification given in the SpecC Language Reference Manual. We mainly see our formal semantics in three application areas. First, it can be taken as a high-level, pseudo code-oriented specification for the implementation of a SpecC simulator which is outlined in a separate section. Second, it is a concise, unambiguous description for documentation and standardization. Finally, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets.

Emulation of CMS systems is an interesting approach to complete the validation of new digital control unit and to perform the diagnosis tasks. However to be efficient, the emulator have to run in real time in order to reproduce exactly the physical process functioning.
     Today, realization of this emulator is not possible using standard electronic components. Therefore, we oriented our work to the development of new embedded systems specific to these applications of emulation.
     This report describes the design of this emulator employing the system-level design methodology developed at CECS-UC Irvine (SpecC methodology). Starting from the abstract executable specification written in SpecC language, different design alternatives concerning the system architecture (components and communications) are explored and the emulator is gradually refined and mapped to a final communication model. This model can then be used with backend tools for implementation and manufacturing. For illustration of this approach, we discuss at the end of this report the case of a DC system emulator and we describe in details the different stages undergone.

Today, control algorithms are being more and more sophisticated due to the customer and governments demands for lower cost, greater reliability, greater accuracy and environment requirements (power consumption, emitted radiation,&). Then, real-time implementation of these algorithms becomes a difficult task and needs more and more specific hardware systems with dedicated processors and usually systems-on-chip (SOCs). With the ever-increasing complexity and time-to-market pressures in the design of these specific control systems, a well design methodology is more than even necessary.
     In this report we describe the application of the SpecC system-level design methodology (developed at the CAD Lab, UC Irvine) to the design of control systems for power electronics and electric drives. We first begin with an executable specification model in SpecC and then discuss the refinement of this model into architecture model, which accurately reflects the system architecture. At this stage, we discuss different solutions according to the application complexity and constraints. Based on the studied architecture models, communication protocols between the system components are defined and communication models are developed. In this report, we discuss the case of a DC system Control and describe in details different stages undergone. Generalization to others systems can be done easily using the same steps and transformations.

Today, the shortest time-to-market in the electric drives industries is being a pressing requirement, consequently development time of new algorithms and new control systems and debugging them must be minimized. This requirement can be satisfied only by using a well-defined System-level design methodology and by reducing the migration time between the algorithm development language and the hardware specification language.
     In this report, we propose to use the SpecC language for the development (specification and validation) of new control algorithms. This includes the specification of the control systems (algorithms and I/O interfaces) in SpecC and its validation by simulation using a SpecC specification model of the process under control.
     This new approach will allow designers to implement easily the retained specification according to the SpecC methodology. Indeed, the same language (SpecC) is used for the study of new control systems and their design and implementation.
     We first begin with a brief presentation of the electric drives and of the SpecC language. Then, we discuss the specification models in SpecC of the whole system including the control unit and the process under control. We illustrate this approach by an application example of a DC system. Finally, we present the main advantages of the SpecC language in the development of new control systems.

Bus-based architecture has better performance than mux-based architecture in large design. In this paper we introduce interconnection binding in a new RTL design methodology. The proposed methodology uses the bus-based architecture and supports pipelined /multi-cycle operations and storage units. By using the tools supporting our methodology, the user can explore the bus-based architecture design space efficiently.

In this report, we present the implementation of storage binding which is one key task in high-level (RTL) synthesis. In previous related works, storage binding is based on isolated register, or uses 0-1 integer linear programming (ILP) for multiple port memories to get optimal result. In this report, we introduce two new approaches that use clique-partitioning algorithm and grouping method to map variables into register files and memories that are normally used in industry.

This report describes the function binding algorithm in RTL synthesis. It describes the RTL design methodology and implement our function binding algorithms in our RTL design refine tool. We proposed two algorithms here, one algorithm is based on the clique partitioning algorithm and the other is based on the seed constructive based algorithm. Our algorithms are resource constraint algorithm and they are focused to minimize the cost ofinterconnections needed for the datapath and can be performed at different RTL refine steps.

This report describes the development of a High-Level Specification Model of the Enhanced Full Rate (EFR) Vocoder. The EFR Vocoder is a complex speech compression algorithm which is widely used in cellular telephone systems. The Vocoder Specification Model is based on the bit-exact simulation code provided by the ETSI and was written in the SpecC language. A detailed analysis of the simulation code was performed, followed by the development of the Vocoder behaviors in the specification language. An IP Distribution Model of the Vocoder was also developed. The report concludes with an analysis of the suitability of the SpecC language for this project.

In this report we present the implementation of a C++ class library aimed at providing basic support for modeling RTL semantics in C++. We first review the inherent features of the RTL modeling in a formal FSMD approach. The corresponding C++ implementation for non-pipelined state-based (Moore) machine is given with the illustration of its usage for two examples.

This document describes the development of RESpecCT, a refinement and exploration-tool for the SpecC technology. RESpecCT is a graphical tool which assists the designer starting from the functional or specification model of the design in refining it using the SpecC methodology through different levels to the implementation- or register transfer-level. It visualizes information in a way to simplify the process of taking decisions about details of the design, gives these decisions to refinement tools and visualizes their results.