UCI Cadlab
Technical Reports 1997


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Postscript TR-97-47

Jon Kleinsmith, Jianwen Zhu and Daniel D. Gajski,
"ATM Modeling Example for SpecGen Evaluation,"
UC Irvine, Technical Report ICS-TR-97-47, October 1997.

In this report we discuss the specification of an ATM cell filter. A behavioral model of the filter is supplied using two specification languages, VHDL, and SpecC, a new language under development by the CADLAB at the University of California, Irvine. A description of the functionality of the filter model is supplied in addition to language features and problems encountered during the specification process. This model is to be used as an example for the evaluation of the SpecGen system, a simulation and synthesis environment also under development at the CADLAB.


Postscript TR-97-42

En-Shou Chang and Daniel D. Gajski,
"A generic binding model for concurrently optimizing interconnection and functional units,"
UC Irvine, Technical Report ICS-TR-97-42, October 1997.

A generic binding model which can provide complete information for binding task is presented in this paper. With information provided by this model, people can do interconnection optimization concurrently with operation and variable binding, as well as find better combination of FUs. Our method is not only much faster but also can obtain better or competitive binding than complex previous works.


Postscript TR-97-37

Peter Grun, Nikil Dutt and Florin Balasa,
"System Level Memory Size Estimation,"
UC Irvine, Technical Report ICS-TR-97-37, September 1997.

DSP applications, such as image, voice, and video processing are characterized by large multi-dimensional arrays, accessed from multiple nested loops. The cost and performance of the final implementation of such designs is dominated by the background storage. To optimize the memory size nd the memory accesses, they have to be consideredat an early design stage. We propose a fast memory size estimation method for a parallel procedural represen-tation, which can trade-off computation time against accuracy. This technique is presented in the context of a Hardware/Software exploration environment.


Postscript TR-97-28

Hartej Singh and Daniel D. Gajski,
"A Design Methodology for Behavioral Level Power Exploration: Implementation and Experiments,"
UC Irvine, Technical Report ICS-TR-97-28.

This work describes an integrated design methodology focusing on power exploration at behavioral level. We present a behavioral-level tool for architecture selection and power estimation within the SpecSyn [GVNG94] environment. Power analysis is done in both steps; it is approximate in the former and detailed in the latter. A combination of empirical and analytical approaches is used for power estimation. We provide several case studies of common benchmarks to illustrate the design methodology as also its interactive and efficient nature that enables fuller design space exploration. We evaluate power versus performance trade-offs for different implementations of each example, using our tool. An important premise for this work is accurate characterisation of resource library for power.


Postscript TR-97-26

Daniel D. Gajski, Jianwen Zhu, Rainer Doemer,
"Essential Issues in Codesign,"
UC Irvine, Technical Report ICS-TR-97-26, June 1997.

I n this report we discuss the main models of computation, the basic types of architectures, and language features needed to specify systems. We also give an overview of a generic methodology for designing systems, that include software and hardware parts, from executable specifications.


Postscript TR-97-16

Jianwen Zhu, Rainer Doemer, Daniel D. Gajski,
"Syntax and Semantics of the SpecC+ Language,"
UC Irvine, Technical Report ICS-TR-97-16, April 1997.

In this paper, we describe the goals for the development of an executable modeling language in the context of a homogeneous methodology featuring the synthesis, reuse and validation flow. A C based language called SpecC+ is proposed as an attempt to achieve these goals. The syntax and semantics of the language is presented and compared with existing HDLs and we conclude it is conceptually more abstract, syntactically simpler, and semantically richer.


Postscript TR-97-15

Daniel D. Gajski, Jianwen Zhu, Rainer Doemer,
"The SpecC+ Language,"
UC Irvine, Technical Report ICS-TR-97-15, April 15, 1997.

In this report, we discuss the characteristicss necessary for specifying embedded hardward-software systems. We describe the constructs needed to capture these characteristics and propose a new C based specification language to describe heterogeneous embedded systems.


Postscript TR-97-14

Jon Kleinsmith, Tatsuya Umezaki, Zhuzhen Kang and Daniel Gajski,
"Co-Design Methodology for ATM Applications Domain,"
UC Irvine, Technical Report ICS-TR-97-14, January 1997.

With the recent explosion of ATM technologies, continuing increases in design complexity and shortened time-to-market demands, new design methodologies coupled with powerful CAD tools are becoming necessary to keep abreast with consumer need in this high-performance/memory intensive application area. Using a system-level approach to design, we demonstrate that a significantly shorter design cycle may be achieved. This methodology is explained on the example of an ATM filter.


Last update: March 25, 1999 by A. Gerstlauer (gerstl@cecs.uci.edu).