UCI Cadlab
Technical Reports 1996


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Postscript TR-96-49

En-Shou Chang and Daniel D. Gajski,
"A connection-oriented binding model for binding algorithms,"
UC Irvine, Technical Report ICS-TR-96-49, Oct 1996

A new binding model which can formulate any architectures is presented in this paper. Several simple algorithms which employ this model are proposed to demonstrate the performance on this model. Experimental results show that these algorithms though are simple yet can obtain better results than previous complex algorithms. In addition, exchanging sources of functional units and sharing functional units, which can improve synthesized results by way of reducing MUX inputs required, are also discussed in this paper.


Postscript TR-96-44

Hartej Singh and Daniel D. Gajski,
"A Design Methodology for Behavioral Level Power Exploration,"
UC Irvine, Technical Report ICS-TR-96-44, Oct 1996

This report describes an integrated design methodology focusing on power exploration at the behavioral level. The design process is iterative and based on designer interaction. Scheduling and power estimation are the two major components in the design process. Power analysis is done in both steps. It is approximate in the first, but detailed in the second step. A combination of empirical and analytical approaches is used for power estimation. Evaluation of power performance trade-offs is done for different implementations for a given behavioral specification.


Postscript TR-96-41

Daniel D. Gajski, Peter Grun, Wenwei Pan and Smita Bakshi,
"Design Exploration for Pipelined IDCT,"
UC Irvine, Technical Report ICS-TR-96-41, September 1996.

ASICs for video compression systems have stringent timing requirements. For example, according to the MPEG standard, the through put of the MPEG decoder is 4115ns. This performance cannot be achieved without efficient pipelining. In this report, we explore the pipelined designs for the Inverse Discrete Cosine Transform (IDCT) which is a critical part of the MPEG decoder. We also transform the algorithm to minimize the memory requirement. We have implemented both the original and memory-optimized algorithms at the RT level, using our realistic library. The behavioral descriptions for both designs are given in the appendix.


Postscript TR-96-34

Wenwei Pan, Peter Grun, Daniel D. Gajski,
"Behavioral Exploration with RTL Library,"
UC Irvine, Technical Report ICS-TR-96-34, July 1996.

Behavioral synthesis that takes into consideration real components as well as timing constraints is necessary for the design of today's ASIC chips. In this report, we give a methodology for design space exploration under timing constraints. To illustrate our proposed methodology, we also give several designs that implement a Square Root Algorithm. We compare these designs and give their behavioral and structural description in the Appendix.


Postscript TR-96-29

Daniel D. Gajski, Tadatoshi Ishii, Viraphol Chaiyakul, Hsiao-Ping Juan and Tedd Hadley,
"A Design Methodology and Environment for Interactive Behavioral Synthesis,"
UC Irvine, Technical Report ICS-TR-96-29, June 1996.

Due to recent increases in chip complexity, behavioral synthesis has become an important area of research and company interest. However, there has been market resistance to the automatic behavioral synthesis approach for two reasons. It often produces results inferior to manual designs, and it allows only minimal user control. To overcome these hurdles, we present a design methodology for human interaction in design synthesis, which, in contrast to the automatic synthesis approach, gives the human designer fine-grain control over synthesis tasks, and continually supplies feedback in the form of quality measures so that the user can make informed design-related decisions. To confirm the feasibility of the proposed design methodology and to demonstrate its power and flexibility, we also present the Interactive Synthesis Environment (ISE), a working software environment comprising design views, quality measure feedback, and synthesis algorithms.


Postscript TR-96-19

En-Shou Chang and Daniel D. Gajski,
"Software Performance Estimation for Toshiba TLCS-R3900,"
UC Irvine, Technical Report ICS-TR-96-19, May 1996.

This report contains information about software performance of Toshiba TLCS-R3900 RISC processor evaluated by a software estimation technique proposed by J. Gong et. al. This technique decomposes the program into basic block then evaluates total execution time by analysis execution flow. The execution time of basic block is computed by compiling subprogram into generic instructions then mapping to real instruction. In addition, we analyze the pipeline stall phenomenon for TLCS-R3900. A processor profile is proposed to count the effects. Based on this generic estimation model, our estimator can produce accurate estimation without large computation time and precious resource, such as compilers or simulators for each processor.


Postscript TR-96-08

Hsiao-ping Juan, Daniel D. Gajski and Viraphol Chaiyakul,
"Clock-Driven Performance Optimization in Interactive Behavioral Synthesis,"
UC Irvine, Technical Report ICS-TR-96-08, April 1996.

In interactive behavioral synthesis, the designer can control the design process at every stage, including modifying the schedule of the design to improve its performance. In this report, we present a methodology for performance optimization in interactive behavioral synthesis. Also proposed in this report are several quality metrics and hints that can assist the user in utilizing the proposed methodology. When the user is optimizing the performance of the design, one important decision is the selection of a clock period. We have developed an algorithm to estimate the effect of different clock periods on the execution time of the design. This algorithm can be used to facilitate clock period selection by the user in order to optimize the performance of the design. We have tested our methodology on several benchmarks. The experimental results support the proposed methodology by demonstrating an average improvement of 46.2% in design performance.


Postscript TR-96-01

Hsiao-Ping Juan, Daniel D. Gajski and Smita Bakshi,
"Clock Optimization for High-Performance Pipelined Design,"
UC Irvine, Technical Report ICS-TR-96-01.

In order to reduce the design cost of pipelined systems, resources may be shared by operations within and across different pipe stages. In order to maximize resource sharing, a crucial decision is the selection of a clock period, since a bad choice can adversely affect the performance and cost of the design. In this report, we present an algorithm to select a clock period that attempts to minimize design area while satisfying a given throughput constraint. Experimental results on several examples demonstrate the quality of our selection algorithm and the benefit of allowing resource sharing across pipe stages.


Last update: March 25, 1999 by A. Gerstlauer (gerstl@cecs.uci.edu).