UCI Cadlab
Technical Reports 1995


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Postscript TR-95-57

En-Shou Chang and Daniel D. Gajski and Sanjiv Narayan,
"An optimal clock period selection method based on slack minimization criteria,"
UC Irvine, Technical Report ICS-TR-95-57, December 1995.

An important decision in synthesizing a hardware implementation from a behavioral description is selecting the clock period to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock period explicitly or require that the delays of the operators used in the design be specified in multiples of the clock period. An unfavorable choice of the clock period could result in operations being idle for a large portion of the clock period, and consequently, affect the performance of the synthesized design. In this paper, we demonstrate the effect of clock slack on the performance of designs and present an algorithm to find a slack-minimal clock period. We prove the optimality of our method and apply it to several examples to demonstrate its effectiveness in maximizing design performance.


Postscript TR-95-34

En-Shou Chang,
"An optimal slack minimization method,"
UC Irvine, Technical Report ICS-TR-95-34, 1995

When synthesizing a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operation into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be specified in multiples of a clock cycle. A bad choice of the clock cycle could adversely affect the performance of the synthesized design. We present mathematical proofs of setting clock cycle length with zero clock slack and an algorithm for estimating the system clock based on a clock slack minimization criteria. This algorithm guarantee the minimum average clock slack.


Postscript TR-95-25

Daniel D. Gajski and Hsiao-Ping Juan,
"A Design Methodology for Interactive Behavioral Synthesis,"
UC Irvine, Technical Report ICS-TR-95-25, July 1995.

Due to the recent increases in design complexity, behavioral synthesis has become an important area of research and company interest. However, there has been market resistance to accepting the automatic behavioral synthesis approach as a practical solution in general because, first, it often produces results inferior to manual designs, and second, it allows only minimum user control. To develop a feasible approach for behavioral synthesis to overcome the hurdles faced by the automatic approach, we propose interactive behavioral synthesis, which attempts to maximally utilize the human designer's insights. Using interactive behavioral synthesis, the users can control the design process, observe the effects of design decisions, and manually override synthesis algorithms at will. In this report, we present a design methodology as how the user interacts with an interactive behavioral synthesis system, which in contrast to an automatic synthesis system, enables the human designer fine-grain control over each synthesis task and continually supplies feedback in the form of quality measures so that the user can make informed design-related decisions. To demonstrate the proposed design methodology, we also present in this report a walk-through square-root approximation (SRA) example.


Postscript TR-95-20

Chu-Yi Huang and Daniel D. Gajski,
"Software Performance Estimation for Pipeline and Superscalar Processors,"
UC Irvine, Technical Report ICS-TR-95-20, June 1995.


Postscript TR-95-03

Smita Baskshi and Daniel D. Gajski,
"A Memory Selection Algorithm for High-Performance Pipelines,"
UC Irvine, Technical Report ICS-TR-95-03, Jan 1995.

In order to perform high-throughput DSP computations, that are predominantly vector or array based, it is essential that the memory organization satisfy both the storage and the performance requirements of the design. In this report, we present an algorithm to select a memory organization, in addition to selecting a pipeline and other datapath components, given performance constraints. We also conduct experiments to give a quantitative measure of the impact of memory selection on DSP design.


Last update: March 25, 1999 by A. Gerstlauer (gerstl@cecs.uci.edu).