UCI Cadlab
Journal Papers


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Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski,
"An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors,"
IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 16, no. 4, pp. 466-475, April 2008.

Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button type synthesis is not accepted by many designers. Interactive design with assistance of algorithms and tools can be more effective if it provides control to the steps of synthesis. In this paper, we propose an interactive RTL design environment which enables designers to control the design steps and to integrate hardware components into a system. Our design environment is targeting a generic RTL processor architecture and supporting pipelining, multicycling, and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.



Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel D. Gajski,
"Automatic Layer-Based Generation of System-On-Chip Bus Communication Models,"
IEEE Transactions on Design Computer-Aided of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1676-1687, September 2007.

With growing market pressures and rising system complexities, automated system-level communication design with efficient design space exploration capabilities is becoming increasingly important. At the same time, customized network-oriented communication architectures become necessary in enabling a high-performance communication among the system components. To this end, corresponding communication design flows that are supported by efficient design automation techniques need to be developed. In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures. Our approach supports a two-stage design flow using automated model refinement toward custom heterogeneous communication networks. Starting from an abstract specification of the desired communication channels, our environment automatically generates tailored network models at various levels of abstraction. At its core, an automatic layer-based refinement approach is utilized. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Our experimental results show significant productivity gains over a traditional communication design, allowing early and rapid design space exploration.


PDF Postscript itti-98-3

Rainer Dömer, Daniel D. Gajski, Jianwen Zhu,
"Specification and Design of Embedded Systems,"
it+ti magazine, Oldenbourg Verlag, Munich, Germany, no. 3, June 1998.

With the rising complexity of digital designs and the deep sub-micron era right ahead, the specification and the design of embedded systems has to move to higher levels of abstraction. Co-design, the design of systems involving both hardware and software parts, consists of a set of refinement tasks that map an abstract specification of the design onto the intended system architecture. This article describes a generic co-design methodology including specification of the design at a high level of abstraction and step-wise refinement.


Postscript todaes-96-3

En-Shou Chang, Daniel D. Gajski, Sanjiv Narayan
"An Optimal Clock Period Selection Method Based on Slack Minimization Criteria,"
ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 3, pp. 352-370, July 1996.

An important decision in synthesizing a hardware implementation from a behavioral descrip tion is selecting the clock period to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock period explicitly or require that the delays of the operators used in the design be specified in multiples of the clock period. An unfavorable choice of clock period could result in operations being idle for a large portion of the clock period and, consequently, affect the performance of the synthesized design. In this article, we demonstrate the effect of clock slack on the performance of designs and present an algorithm to find a slack-minimal clock period. We prove the optimality of our method and apply it to several examples to demonstrate its effectiveness in maximizing design performance.


Last update: April 7, 1999 by A. Gerstlauer (gerstl@cecs.uci.edu).