Professor Nader Bagherzadeh’s Research

Nader Bagherzadeh is currently with University of California Irvine (UCI), where he is a Professor of Electrical Engineering and Computer Science with the Donald Bren School of Information and Computer Science. Bagherzadeh is interested in hardware, software, and VLSI design of low-power and high performance computer systems for applications in mobile systems, computer graphics processing, 3D integrated circuits, memory structures, and integrated sensors. His current research area is involved with the design of next generation System-on-Chip (SoC) based on the notion of Network-on-Chip (NoC) architecture for connecting 100’s of cores on the same die. He has worked on low power routers, wired and wireless on-chip communication, mapping and scheduling algorithms, as well as the fault-tolerance aspects of the NoC architectures. For details about past research please visit http://gram.eng.uci.edu/comp.arch/nader2.html

Research Focus:

Chip Multi-Processor Platform

• Homogeneous/Heterogeneous CMP

 

Interconnection Network

• High performance Router Architecture
• General Network Interface
• GALS Architecture
• Wireless NoC

 

High Performance Processing Element

• General Purpose 32bit RISC Core

 

Task Scheduling

• Power Aware Scheduling
• Divisible Load Theory
• Intelligent Scheduling

 

NoC Tool Chain

• System Model
• Application Model
• NoC Simulator

 

Power Aware Design

• Power Aware Architecture
• Power Aware Scheduling