Journal Articles

Journal of Information Science and Engineering (JISE)

Yi-Hsuan Lin, Tung-Mei Ko, Tyng-Ruey Chuang, Kwei-Jay Lin: Open Source Licenses and the Creative Commons Framework: License Selection and Comparison. J. Inf. Sci. Eng. 22(1): 1-17 (2006)


Information Systems Frontiers (ISF)

Jane Yung-jen Hsu, Kwei-Jay Lin, Tsung-Hsiang Chang, Chien-Ju Ho, Han-Shen Huang, Wan-rong Jih: Parameter learning of personalized trust models in broker-based distributed trust management. Information Systems Frontiers 8(4): 321-333 (2006)


International Journal of Parallel Programming (IJPP)

Ian G. Harris, Franco Fummi: Guest Editor’s Introduction. International Journal of Parallel Programming (IJPP) 34(1):1-2 (2006)

Samar Abdi, Daniel Gajski: Verification of System Level Model Transformations. International Journal of Parallel Programming (IJPP) 34(1):29-59 (2006)


IEEE Computer

Martin Bichler, Kwei-Jay Lin: Service-Oriented Computing. IEEE Computer 39(3): 99-101 (2006)


Electronic Notes in Theoretical Computer Science (ENTCS)

Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta, Jean-Pierre Talpin: A Verification Approach for GALS Integration of Synchronous Components. Electr. Notes Theor. Comput. Sci. 146(2): 105-131 (2006)


Computer Architecture Letters (CAL)

Jean-Luc Gaudiot, Yale N. Patt, Kevin Skadron: Foreword. Computer Architecture Letters 5(2): (2006)


Communications for the ACM (CACM)

Mark D. Hill, Jean-Luc Gaudiot, Mary W. Hall, Joe Marks, Paolo Prinetto, Donna Baglio: A Wiki for discussing and promoting best practices in research. Commun. ACM 49(9): 63-64 (2006)


Parallel Computing

Won Woo Ro and Jean-Luc Gaudiot, “A Complexity-Effective Microprocessor Design with Decoupled Dispatch Queues,” to appear in Parallel Computing, in press (2008).


Journal on Applied Signal Processing (EURASIP)

S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh, “Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System,” to appear in Journal on Applied Signal Processing.


International Journal of Time-Critical Computing Systems

G. Madl, S. Abdelwahed, and D. Schmidt, “Verifying Distributed Real-time Properties of Embedded Systems via Graph Transformations and Model Checking,” International Journal of Time-Critical Computing Systems, invited paper, 2005.
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International Journal of Parallel Programming (IJPP)

Hsiao-Hsi Wang, Kuan-Ching Li, Ssu-Hsuan Lu, Chun-Chieh Yang, Jean-Luc Gaudiot , “Design and Implementation of an Agent Home Scheme Strategy for Prefetch-Based DSM Systems,”International Journal of Parallel Programming (IJPP), Springer.


International Journal of Embedded Systems

P. Mishra, N. Dutt, N. Krishnamurthy, M. Abadir, “A Methodology for Validation of Microprocessors using Symbolic Simulation,” International Journal of Embedded SystemsIssue 1/2, 2005.

J. Lee, K. Choi, and N. Dutt, “Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures,” International Journal of Embedded Systems, Issue 7, 2005.


Image and Vision Computing

Weisheng Duan, Falko Kuester, Jean-Luc Gaudiot, and Omar Hammami, “Automatic Object and Image Alignment using Fourier Descriptors,” to appear in Image and Vision Computing, in press (2008).


IEEE/ACM Digest of Technical Papers for the International Conference on Computer Aided Design

T. Givargis, F. Vahid, and J. Henkel, “System-Level Exploration for Pareto-Optimal Configurations in Parameterized System-on-Chip,” IEEE/ACM Digest of Technical Papers for the International Conference on Computer Aided Design (ICCAD 2001), November 4-8, 2001, pp 25-30.


IEEE Transactions on VLSI

D. Shin, A. Gerstlauer, R. Doemer, D. Gajski, “An Interactive Design Environment for C-based High-level Synthesis of RTL Processors,” IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 4, pp. 466-475, April 2008.

P. Heydari and R. Mohanavelu, “Design of Ultra High-Speed Low-Voltage CMOS CML buffers and Latches,” to appear in IEEE Trans. on VLSI Systems2004.
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P. Heydari and M. Pedram, “Ground Bounce in Digital VLSI Circuits,” IEEE Trans. on VLSI Systems, Vol. 11, No. 2, pp 180-193, April 2003.
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J. Zhu, D. D. Gajski, ” An Ultra-Fast Instruction Set Simulator,” IEEE Transactions on VLSI, Vol. 10, No. 3, June 2002, pp 363-373

S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, “FABSYN: Floorplan-aware Bus Architecture Synthesis,” IEEE Trans. on VLSI, Vol 14, No. 3, March 2006, pp 241-253.
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